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docs: hyperlink 50x claim to VCN Pipeline compression table

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Brandon Schneider 2026-05-30 20:55:06 -05:00
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6-Documentation/docs/WIKI.md
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> Comprehensive architecture reference — May 30, 2026
The Research Stack is a capability-adaptive compute fabric that turns every device in a Tailscale mesh — from NVIDIA GPUs to ESP32 microcontrollers — into a unified distributed compute cluster. Formal proofs live in Lean 4; Python shims handle I/O at the boundary; Ray schedules work across the mesh; and a custom VCN compression pipeline achieves **50× bandwidth reduction** for cross-node data transfers.
The Research Stack is a capability-adaptive compute fabric that turns every device in a Tailscale mesh — from NVIDIA GPUs to ESP32 microcontrollers — into a unified distributed compute cluster. Formal proofs live in Lean 4; Python shims handle I/O at the boundary; Ray schedules work across the mesh; and a custom VCN compression pipeline achieves [**50× bandwidth reduction**](#4-vcn-pipeline) for cross-node data transfers.
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docs/WIKI.md
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@ -2,7 +2,7 @@
> Comprehensive architecture reference — May 30, 2026
The Research Stack is a capability-adaptive compute fabric that turns every device in a Tailscale mesh — from NVIDIA GPUs to ESP32 microcontrollers — into a unified distributed compute cluster. Formal proofs live in Lean 4; Python shims handle I/O at the boundary; Ray schedules work across the mesh; and a custom VCN compression pipeline achieves **50× bandwidth reduction** for cross-node data transfers.
The Research Stack is a capability-adaptive compute fabric that turns every device in a Tailscale mesh — from NVIDIA GPUs to ESP32 microcontrollers — into a unified distributed compute cluster. Formal proofs live in Lean 4; Python shims handle I/O at the boundary; Ray schedules work across the mesh; and a custom VCN compression pipeline achieves [**50× bandwidth reduction**](#4-vcn-pipeline) for cross-node data transfers.
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