Brandon Schneider
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7237b2e09b
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feat: vectorized delta+RLE via copy-if pattern (3.3x faster, 2.5x smaller)
Inspired by loonatick-src vectorized copy_if analysis:
- VPCOMPRESSD memory-dest = 144 microcode uops (40x bottleneck)
- Register-dest compress + regular store = 10-40x faster
Applied to VCN pipeline:
- numpy vectorized delta (np.diff) + copy-if (nonzero mask)
- RLE on filtered stream = concentrated runs = better compression
- Falls back to scalar if numpy unavailable or data < 1024 bytes
Benchmark (800KB random data):
Scalar: 132.8ms, 499KB output (0.62 ratio)
Vectorized: 40.2ms, 200KB output (0.25 ratio)
Speedup: 3.3x, compression: 2.5x smaller
Wire: delta_rle_encode_vectorized() replaces delta_rle_encode() in pipeline
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2026-05-29 02:24:55 -05:00 |
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Brandon Schneider
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53e38e4c71
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feat: 12 math enhancements — Q16 LUT, braid VCN encoder, FPGA Verilog, FFT, crypto
Pipeline:
- q16_lut_vcn.py: Q16_16 LUT generation + VCN frame encoding (8 ops)
- braid_vcn_encoder.py: Delta+RLE → RS ECC → ChaCha20 → VCN → MKV
- braid_search.py: Sidon set slots, soliton search, QUBO optimization
- test_braid_pipeline.py: 67 tests covering full round-trip
WebGPU/Scripts:
- braid_fft.wgsl: Cooley-Tukey radix-2 FFT on phase vectors
- reed_solomon_vcn.py: Reed-Solomon ECC for VCN frame data
- chacha20_braid.py: ChaCha20 encryption + key derivation
- polynomial_commitment.py: KZG scheme for receipt verification
Lean:
- BraidBitwiseODE.lean: XOR crossing, O(1) integration, 2 proved theorems
FPGA (Tang Nano 9K):
- q16_lut_core.v: 8-op arithmetic, 2-stage pipeline, BRAM reciprocal
- braid_crossing_core.v: 4-stage crossing residual, 7 Q16 instances
- Testbenches with edge cases + VCD dumps
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2026-05-28 14:49:26 -05:00 |
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