Brandon Schneider
aba1fba7ad
fix(adversarial-review): resolve 35 critical coding bugs across 8 subsystems
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Security & correctness fixes from full adversarial review:
Lean (7 fixes):
- FixedPoint.lean: guard false theorem with n > 0 precondition
- QFactor.lean: remove double-scaling error in energy decrease
- AVMIsa/Step.lean: implement addSatQ16/subSatQ16 primitives
- BraidEigensolid.lean: fix crossStep second output argument swap
- SSMS.lean: complete ACI preservation proof (with rounding caveat)
- HouseholderQR.lean: add n > 0 precondition to spectral theorem
Verilog (7 fixes):
- q16_lut_core.v: fix multiply shift (16 → 32 bits)
- q16_lut_top.v: fix valid bit (0 → 1)
- cff_accelerator.v: fix SHA-256 padding (len < 448 check)
- research_stack_top.v: fix trigger aliasing (unique counters)
- Blitter6502OISC_small.v: fix address width (15 → 16 bits)
- spatial_hash_bram.v: add OOB write guard
- tmr_oepi_safety_fsm.v: fix double-increment race
WGSL (6 fixes):
- shaders.wgsl: atomicAdd for concurrent writes
- frustration_qubo.wgsl: double-buffer + CAS loop
- braid_fft.wgsl: workgroupBarrier synchronization
- burgers_scar_filter.wgsl: atomic E_bins array
Rust (9 fixes):
- thermodynamic.rs: Arc::from_raw → Arc::clone (double-free)
- thermodynamic.rs: Box::into_raw → Box (leak)
- tools/src/lib.rs: shell injection → shlex.quote
- ene-node/src/lib.rs: LRU caps, constant-time HMAC, peer caps
Python (6 fixes):
- similarity/__init__.py: pickle.load → RestrictedUnpickler
- AI-Feynman: torch.load → weights_only=True (14 calls)
- fetch_arxiv.py, fetch_s2.py: eval → ast.literal_eval
- topology.py: os.system → shutil.copy2
- SSH pipe: os.system → base64 pipe
Build: lake build 3572 jobs, 0 errors
2026-05-31 23:38:03 -05:00
Brandon Schneider
ba203ca971
feat: spatial hash grid — GPU-style particle physics (Python + FPGA)
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Ported from ScaleSpaceSynth (WebGPU particle simulator):
- 64×64×64 spatial hash, 32 particles/cell, lock-free insertion
- Curl noise: divergence-free 3D turbulence
- Pairwise forces: attractive (ratio>0.15) + repulsive (ratio<=0.15)
- Trilinear density interpolation
- HalfLife particle lifecycle
- Q16_16 encode/decode for VCN transport
Python (spatial_hash_grid.py): 6/6 tests pass
10K particles, neighbor query, forces, 100 sim steps, curl noise verified
FPGA (spatial_hash_bram.v):
16×16×16 grid, dual-port BRAM, 27-cycle neighbor scan
Density → voltage mode selector (STORE/COMPUTE/APPROX/MORPHIC)
Integrated into research_stack_top.v
Same pattern as ScaleSpaceSynth GPU:
GPU: atomicAdd for lock-free cell assignment
FPGA: BRAM read-modify-write for cell assignment
Ray: content-addressed ObjectRef for lock-free reads
All: partition space → compute density → find structure at multiple scales
2026-05-30 01:25:19 -05:00
Brandon Schneider
9f304abab0
feat: fractal dimension — DBC algorithm (Python + FPGA)
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Paper: 'Ultra-fast computation of fractal dimension for RGB images'
(Pattern Analysis and Applications, 2025)
Python (fractal_dimension.py):
- DBC algorithm with numpy vectorization (29x faster than scalar)
- fd_compress_hint: FD → voltage mode (STORE/COMPUTE/APPROX/MORPHIC)
- 7/7 tests pass (Sierpinski, random, gradient, checkerboard, fBm, constant, RGB)
- Q16_16 integer arithmetic internally
FPGA (fractal_box_counter.v + fractal_fd_selector.v):
- 5-state FSM: IDLE → COLLECT → FINALIZE → STORE_LOG → REGRESS → DONE
- 8 power-of-two scales (2, 4, 8, ..., 256)
- Linear regression via Q16_16 64-bit arithmetic
- FD clamped to [1.0, 3.0] in Q16_16
- Selector: FD < 2.3 → STORE, < 2.6 → COMPUTE, < 2.9 → APPROX, >= 2.9 → MORPHIC
- Integrated into research_stack_top.v
FD drives adaptive compression:
Low FD (smooth) → STORE mode (minimal compression)
High FD (rough) → MORPHIC mode (aggressive compression)
2026-05-29 20:45:21 -05:00
Brandon Schneider
9596c78ab9
fix: UART bug (retransmit) + auto-start + LED heartbeat + sim verification
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Blitter6502OISC_small.v:
- Added uart_sent flag to prevent UART retransmission
- Verified via Verilator: UART sends exactly one byte on halt
- Test byte: 0xAA (recognizable pattern)
research_stack_top.v:
- Auto-start logic (100ms after reset, no button needed)
- LED shows heartbeat when CPU running, register values on halt
research_stack_tangnano9k.cst:
- uart_tx=17, uart_rx=18 (matches Sparkle reference design)
Simulation results (Verilator):
- uart_test.v: 115 bytes in 300K cycles (continuous TX verified)
- research_stack_top: UART fires after Blitter halt, 0xAA byte sent
- LED pattern changes from IDLE to RUNNING to HALTED
2026-05-28 21:42:11 -05:00
Brandon Schneider
09f2f3044a
feat: unified FPGA bitstream for Tang Nano 9K — BUILD SUCCESSFUL
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research_stack_top.fs (2.0MB) — all modules synthesized:
- Blitter6502OISC (4K memory, SUBTLEQ CPU)
- q16_lut_core (Q16_16 arithmetic, 8 ops)
- blitter_memory_map (8-bit ↔ 32-bit bridge)
- voltage_mode_controller (4 BRAM modes)
- scale_space_bram (Gaussian kernel banks)
- highs_pivot_accelerator (simplex pipeline)
Timing: 195.92 MHz (PASS at 27 MHz target, 7.2x margin)
Device: GW1NR-LV9QN88PC6/I5 (Tang Nano 9K)
To flash: openFPGALoader -b tangnano9k research_stack_top.fs
2026-05-28 16:32:05 -05:00
Brandon Schneider
cd6f09d333
feat: unified FPGA top-level for Tang Nano 9K
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research_stack_top.v: connects all modules
- Blitter6502OISC CPU
- blitter_memory_map (8-bit ↔ 32-bit bridge)
- q16_lut_core (Q16_16 arithmetic, 8 ops)
- voltage_mode_controller (4 BRAM modes)
- scale_space_bram (Gaussian kernel banks)
- highs_pivot_accelerator (simplex pipeline)
- LED output: {cpu_busy, q16_done, voltage_mode, scale_select}
- UART telemetry at 115200 baud
Synthesis running (GW1NR-9C, 27MHz target).
2026-05-28 16:16:54 -05:00
