Devin AI
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a496d8d3ce
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fix(infra): Q16_SCALE int not float, add missing Path/sys imports
- Q16_SCALE: float → int in lib/q16.py (int // float returns float,
breaking Q16_16 integer contract in gccl_waveprobe, vcn_famm_transport)
- qr_spatial_hash.py: sys → _sys (only _sys was imported)
- Add missing 'from pathlib import Path' to 7 files that use Path()
without importing it: test_fpga, compare_tier1_vs_tier2,
generate_avm_gold_trace, burgers_triad_core, hot_path_cold_path,
sabotage_prevention, generate_diat_tables
- hot_path_cold_path.py: also add missing 'import sys'
Co-Authored-By: Allaun Silverfox <bigdataiscoming+9i37y6j2@protonmail.com>
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2026-06-16 01:16:31 +00:00 |
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Devin AI
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e5f04ee6c3
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refactor(infra): extract shared utilities from duplicated code patterns
Create 4-Infrastructure/lib/ with canonical implementations of:
- hashing.py: sha256_bytes, sha256_text, sha256_file
- q16.py: Q16_16 fixed-point constants and arithmetic
- jsonl.py: load_json, load_jsonl, write_jsonl, stable_json, canonical_json_bytes
- fraction_utils.py: Fraction serialization helpers for hardware probes
Refactor 66 files across 4-Infrastructure/{hardware,shim,infra} and
5-Applications/{scripts,tools-scripts,hutter_prize,text-to-cad} to import
from the shared library instead of maintaining local copies.
4-Infrastructure/auto/lib/q16.py now re-exports from lib.q16.
Net: -743 lines (490 added, 1233 removed)
Build: not applicable (Python-only change, py_compile verified on all 71 files)
Co-Authored-By: Allaun Silverfox <bigdataiscoming+9i37y6j2@protonmail.com>
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2026-06-15 02:26:45 +00:00 |
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Brandon Schneider
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9e13946972
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test: FPGA test suite — 12/12 pass
Hardware: bitstream loaded, JTAG alive, UART open, baud rate correct
Modules: Q16 LUT, voltage controller, scale space, HiGHS pivot, memory map, CPU
Integration: full pipeline verified (74ns/op)
UART: ttyUSB1 @ 115384 baud (matches Lean uartBaudDivisor proof)
JTAG: ttyUSB0 @ 115200 baud (FTDI responding)
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2026-05-28 19:57:45 -05:00 |
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