Brandon Schneider
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7884fd074b
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feat: optimized route proof + scale space solver fix
Lean:
- OptimizedRoute.lean: 2-opt route shorter than exactishRoute
optimizedRoute cost: 345147 vs exactishRoute: 401666 (14.1% shorter)
Proofs: optimizedRoute_length, optimizedRoute_shorter, costSavings_positive
All via native_decide. lake build: 3571 jobs, 0 errors.
Python:
- scale_space_solver.py: replaced Gaussian cost smoothing with cluster-based
multi-scale optimization. Single-linkage clustering at each sigma, reduced
TSP on representatives, expand + 2-opt polish. Fixed voltage/scale mapping.
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2026-05-28 15:53:28 -05:00 |
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Brandon Schneider
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e2f3a9e93b
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feat: HiGHS integration, scale space solver, adjugate matrix, FPGA voltage/BRAM modules
HiGHS Optimization:
- qubo_highs.py: QUBO→MIP reformulation via highspy (exact, not approximate)
- solve_route_lp: TSP/VRP assignment relaxation for RouteCost 39-node graph
- scale_space_solver.py: multi-scale optimization (coarse LP → fine MIP)
- Gaussian kernels in Q16_16, voltage↔scale mapping
- alphaproof_loop.py: Ollama → lake build → feedback proof search
Lean Formalization:
- AdjugateMatrix.lean: division-free matrix inversion (291 lines, 3300 jobs, 0 errors)
- det2/det4/det8 via cofactor expansion, all Q16_16
- adjugate, matrixInverse, cayleyTransform
- 7 #eval witnesses all pass
FPGA (Tang Nano 9K):
- voltage_mode_controller.v: 4-mode BRAM (STORE/COMPUTE/APPROX/MORPHIC)
- scale_space_bram.v: 4 Gaussian kernel banks (σ=0.25/0.50/0.75/1.00)
- highs_pivot_accelerator.v: 3-stage pipeline, Q16_16 division, 64-element columns
- blitter_memory_map.v: 8-bit CPU ↔ 32-bit Q16 bridge, full I/O map at $8000
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2026-05-28 15:42:14 -05:00 |
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