Brandon Schneider
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dbf67ab130
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test: FPGA test suite — 12/12 pass
Hardware: bitstream loaded, JTAG alive, UART open, baud rate correct
Modules: Q16 LUT, voltage controller, scale space, HiGHS pivot, memory map, CPU
Integration: full pipeline verified (74ns/op)
UART: ttyUSB1 @ 115384 baud (matches Lean uartBaudDivisor proof)
JTAG: ttyUSB0 @ 115200 baud (FTDI responding)
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2026-05-28 19:57:45 -05:00 |
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