Commit graph

7 commits

Author SHA1 Message Date
Brandon Schneider
4b828e369c ROADMAP.md: correct 9 phantom/stale claims flagged by review agents
**CRITICAL fixes**
- Header: note UNIVERSAL_SUBSTRATE_ROADMAP.md no longer exists on disk;
  add note that TODO_MAP.md may lag this file
- §11: replace dead cross-reference with accurate statement; mark full
  census reconstruction as Phase 0 deliverable
- Phase 0: split into completed infrastructure vs pending Lean work;
  explicitly note `USTSM_State` does not yet exist in any Lean file

**ERROR fixes**
- §1: retract unverified "2,634 models" figure; replace with measured
  1,126 ingested equation rows (source: equations.csv 2026-05-18)
- §6 Invariant 7: clarify Q0_64 universality is a Phase 0-1 design
  goal, not a current enforced fact; note Bind.lean uses Q16_16
  exclusively by design ("all values require integer component for
  gradient computation") — no contradiction, different scopes
- §8: expand Semantics/Semantics description to reflect 946+ entries
  (not a handful of named modules); update §4-Infrastructure/infra/
  description to reflect Rust-only state (Python shims removed)
- §12 Credential Gateway: remove reference to deleted credential_server.py;
  credit rs-surface binary and credential.rs module

**WARNING fixes**
- §10 FPGA Hardware: change  Synthesized → 🔄 Bitstream ready; add
  "live hardware receipt pending" caveat
- Phase 4 heading: rename to clarify concurrent-with-Phases-2-3; add
  explanatory note

**BLOCKED annotation**
- Immediate action #8 (Flash Tang Nano 9K): mark as blocked on physical
  board + USB programmer

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2026-05-19 17:04:45 +00:00
Brandon Schneider
4d715908fd docs: full documentation + roadmap refresh (2026-05-19)
- CHANGELOG: add 2026-05-09 through 2026-05-19 entry covering Lean
  hardening, storage stack, 20+ new gates, physics RG suite
- ROADMAP: update layer model (746 modules, 3529 jobs, 0 errors);
  mark eigensolid_convergence proven; add section 12 (Infrastructure
  & Data Layer) covering ENE RDS, Garage S3, storage agent, devcontainer
- TODO_MAP: add B11 (eigensolid convergence, DONE), Phase I (infra),
  Phase J (adversarial gates); rename old Phase I to Phase K
- README: update Lean module/build counts; add Infrastructure table
- ARCHITECTURE: update L0 row; add repository structure rows for
  ene-rds, storage, devcontainer; add sections 11-13 (Storage &
  Persistence Layer, ENE RDS Workspace, Braid Eigensolid Compressor)
- CONCEPTS: add Braid Eigensolid Compressor, Constrained Agent
  Framework, and Garage S3 Storage Stack concept entries
- 4-Infrastructure/README: rewrite to reflect ENE RDS Rust workspace,
  restic/Garage/rclone storage stack, storage agent, GPU dispatch,
  adversarial harnesses

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2026-05-19 09:12:16 +00:00
Brandon Schneider
de06a85a83 Quarantine sorry blocks, fix RcloneIntegration proof, add ENE wiki re-ingest and ZFS setup.
Lean sorry audit (lake build passes, 3539 jobs):
- FixedPointBridge: 10 sorrys quarantined with TODO(lean-port) — all blocked on
  Float→Q bridge lemmas (Q0_16/Q16_16 round-trip error bounds)
- HyperbolicStateSurface: 3 sorrys quarantined — need Q16_16.sqrt error-bound
  and Q16_16.add_pos_of_pos lemmas
- CostEffectiveVerification: 1 sorry quarantined; also fixed pre-existing
  struct/structure typo, Array.Repr, Real.abs syntax, and Bool/Prop mismatch
- MMRFAMMUnification: 1 sorry quarantined — Array.foldl induction lemma missing
- WaveformTeleport: constantWaveformAtFixedPoint_base native_decide was
  numerically false; replaced with sorry + TODO(lean-port)
- RcloneIntegration: startTask_pending_non_increasing PROVED — only sorry fully
  closed, using List.partition_eq_filter_filter + List.filter_sublist
- DiffusionSNRBias, GPUVerificationMetaprobe, QFactor, SSMS: already properly
  quarantined; verified build passes

Infrastructure additions:
- ene_wiki_body_reingest.py: 5-source priority resolver for ene.wiki_revisions
  text="" gap (TiddlyWiki → filesystem → Notion → package description → stub)
- zfs-pool-setup.sh: stackcache pool (500G sparse vdev) with hot/warm/cold
  thermal-zone dataset hierarchy; requires reboot to 7.0.9-1-cachyos kernel

Docs:
- ROADMAP.md: mark Lean→Verilog/FPGA targets as LONG-TERM in Phase 6
- UNIFIED_SIGNAL_ARCHITECTURE.md: add FPGA-column deferral notice

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2026-05-18 23:01:44 -05:00
Brandon Schneider
a6311ed940 chore: preserve working tree before secure wipe
- Update .gitignore with **/target/ for Rust build artifacts
- Add eval receipts to UniversalBridge.lean (compile-time verification comments)
- Add PCIe Idle-Cycle Compute Harvester to ROADMAP.md
- Clean up deprecated scripts, generated Verilog, and old tools (23 deletions)
- Stage new infrastructure: Xen/Alpine embedded surface, QFOX topology manager
- Stage new probes: boundary activation field, holographic carving
- Stage new applications: finance manager, script roots
- Stage new research spec: PCIe idle-cycle substrate
2026-05-13 17:36:02 -05:00
Brandon Schneider
a99e839bab Track remaining source and documentation inventory 2026-05-11 22:18:31 -05:00
Brandon Schneider
38ddec024d Add RRC projection receipts and roadmap mirrors 2026-05-08 14:50:03 -05:00
Brandon Schneider
0709b298b3 Consolidate research stack updates 2026-05-05 21:09:48 -05:00