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304 lines
11 KiB
Verilog
304 lines
11 KiB
Verilog
// BRAM Partial LUT for Morphic DSP
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// Implements adaptive storage for pattern matching, weights, thresholds
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// Target: Lattice iCE40 HX8K / ECP5
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// Q16.16 fixed-point arithmetic
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`timescale 1ns / 1ps
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// ═══════════════════════════════════════════════════════════════════════════
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// BRAM Partial LUT Module
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// 1024-entry lookup table (10-bit address, 32-bit Q16.16 data)
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// Supports runtime updates via write enable
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// ═══════════════════════════════════════════════════════════════════════════
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module bram_partial_lut (
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input wire clk,
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input wire we, // Write enable
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input wire [9:0] addr, // Address (1024 entries)
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input wire [31:0] din, // Data in (Q16.16)
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output reg [31:0] dout // Data out (Q16.16)
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);
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// BRAM storage (1024 x 32-bit)
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reg [31:0] memory [0:1023];
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// Read/write operation
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always @(posedge clk) begin
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if (we) begin
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memory[addr] <= din; // Write
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end
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dout <= memory[addr]; // Read (registered output)
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end
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// BRAM Partial LUT with Morphic Scalar Integration
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// Morphic scalar amplitudes drive BRAM updates
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// ═══════════════════════════════════════════════════════════════════════════
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module bram_partial_lut_morphic (
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input wire clk,
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input wire we, // Write enable
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input wire [9:0] addr, // Address
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input wire [31:0] din, // Data in
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output reg [31:0] dout, // Data out
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input wire update_enable, // Morphic scalar update enable
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input signed [31:0] morphic_amplitude, // Morphic scalar amplitude
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input wire [9:0] pattern_addr, // Pattern address for matching
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output wire [31:0] pattern_match_threshold // Pattern match threshold output
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);
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// BRAM storage
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reg [31:0] memory [0:1023];
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// Morphic scalar update logic
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wire signed [31:0] updated_value;
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wire signed [31:0] current_value;
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wire signed [31:0] amplitude_scaled;
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// Scale morphic amplitude for BRAM update
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assign amplitude_scaled = morphic_amplitude >>> 8; // Scale down by 256
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// Update calculation: new_value = old_value + scaled_amplitude
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assign updated_value = current_value + amplitude_scaled;
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// Read current value
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assign current_value = memory[addr];
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// Read/write operation
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always @(posedge clk) begin
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if (we) begin
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if (update_enable) begin
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memory[addr] <= updated_value; // Morphic scalar update
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end else begin
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memory[addr] <= din; // Direct write
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end
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end
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dout <= memory[addr];
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end
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// Pattern match threshold lookup
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assign pattern_match_threshold = memory[pattern_addr];
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// BRAM Partial LUT for Pattern Matching
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// Stores pattern matching thresholds (e.g., 72% match threshold)
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// ═══════════════════════════════════════════════════════════════════════════
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module bram_pattern_match_lut (
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input wire clk,
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input wire we,
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input wire [9:0] pattern_id, // Pattern identifier
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input wire [31:0] match_threshold, // Match threshold (Q16.16, e.g., 0.72 = 72%)
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output reg [31:0] current_threshold,
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output wire match_detected // Pattern match detected
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);
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// BRAM storage for pattern thresholds
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reg [31:0] pattern_thresholds [0:1023];
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always @(posedge clk) begin
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if (we) begin
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pattern_thresholds[pattern_id] <= match_threshold;
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end
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current_threshold <= pattern_thresholds[pattern_id];
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end
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// Simple match detection (threshold >= 0.5)
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localparam signed [31:0] MATCH_THRESHOLD = 32'sh00008000; // 0.5 in Q16.16
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assign match_detected = (current_threshold >= MATCH_THRESHOLD);
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// BRAM Partial LUT Testbench
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// ═══════════════════════════════════════════════════════════════════════════
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module bram_partial_lut_tb;
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reg clk;
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reg we;
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reg [9:0] addr;
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reg [31:0] din;
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wire [31:0] dout;
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// Instantiate BRAM partial LUT
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bram_partial_lut dut (
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.clk(clk),
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.we(we),
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.addr(addr),
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.din(din),
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.dout(dout)
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);
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// Clock generation (50MHz)
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initial clk = 0;
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always #10 clk = ~clk;
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// Test stimulus
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initial begin
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// Initialize
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clk = 0;
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we = 0;
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addr = 10'd0;
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din = 32'd0;
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#20;
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// Write pattern matching threshold (72% = 0.72 in Q16.16)
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#20;
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we = 1;
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addr = 10'd0;
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din = 32'sh0000B851; // 0.72 in Q16.16
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#20;
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we = 0;
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// Read back
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#20;
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addr = 10'd0;
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#20;
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$display("Pattern threshold: %d", dout);
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// Write another threshold (50% = 0.50 in Q16.16)
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#20;
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we = 1;
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addr = 10'd1;
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din = 32'sh00008000; // 0.50 in Q16.16
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#20;
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we = 0;
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// Read back
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#20;
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addr = 10'd1;
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#20;
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$display("Pattern threshold: %d", dout);
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#100;
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$finish;
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end
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// MEMS Microphone Interface (SPH0645)
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// I2S/PDM digital output interface for acoustic input
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// ═══════════════════════════════════════════════════════════════════════════
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module mems_mic_interface (
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input wire clk, // System clock (27MHz)
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input wire mic_clk, // MEMS mic clock (typically 2.4MHz)
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input wire mic_data, // MEMS mic data (PDM or I2S)
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input wire mic_lr, // Left/Right select (I2S only)
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output reg [31:0] audio_sample, // Q16.16 audio sample output
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output reg sample_valid // Sample valid flag
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output reg [9:0] sample_addr // BRAM address for pattern matching
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input wire pattern_we, // Pattern match write enable
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input wire [9:0] pattern_addr, // Pattern match address
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input [31:0] pattern_threshold // Pattern match threshold
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output wire pattern_match // Pattern match detected
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);
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// PDM to PCM conversion (simplified)
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reg [15:0] pdm_accumulator;
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reg [7:0] pdm_counter;
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always @(posedge mic_clk) begin
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pdm_accumulator <= pdm_accumulator + {16'b0, mic_data};
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pdm_counter <= pdm_counter + 1;
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if (pdm_counter == 8'd255) begin
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// Convert to Q16.16 (shift by 16)
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audio_sample <= {pdm_accumulator, 16'b0};
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sample_valid <= 1'b1;
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pdm_accumulator <= 16'b0;
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pdm_counter <= 8'b0;
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end else begin
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sample_valid <= 1'b0;
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end
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end
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// Pattern matching address generation
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assign sample_addr = audio_sample[9:0]; // Use lower 10 bits as address
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// Pattern match detection
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localparam signed [31:0] MATCH_THRESHOLD = 32'sh00008000; // 0.5 in Q16.16
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assign pattern_match = (audio_sample >= MATCH_THRESHOLD);
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// BRAM Partial Lut with Morphic Scalar Testbench
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// ═══════════════════════════════════════════════════════════════════════════
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module bram_partial_lut_morphic_tb;
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reg clk;
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reg we;
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reg [9:0] addr;
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reg [31:0] din;
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wire [31:0] dout;
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reg update_enable;
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reg signed [31:0] morphic_amplitude;
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reg [9:0] pattern_addr;
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wire [31:0] pattern_match_threshold;
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// Instantiate BRAM partial LUT with morphic integration
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bram_partial_lut_morphic dut (
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.clk(clk),
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.we(we),
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.addr(addr),
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.din(din),
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.dout(dout),
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.update_enable(update_enable),
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.morphic_amplitude(morphic_amplitude),
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.pattern_addr(pattern_addr),
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.pattern_match_threshold(pattern_match_threshold)
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);
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// Clock generation (50MHz)
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initial clk = 0;
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always #10 clk = ~clk;
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// Test stimulus
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initial begin
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// Initialize
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clk = 0;
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we = 0;
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addr = 10'd0;
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din = 32'd0;
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update_enable = 0;
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morphic_amplitude = 32'sd0;
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pattern_addr = 10'd0;
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#20;
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// Write initial threshold (72% = 0.72 in Q16.16)
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#20;
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we = 1;
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addr = 10'd0;
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din = 32'sh0000B851;
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#20;
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we = 0;
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// Read back
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#20;
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addr = 10'd0;
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#20;
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$display("Initial threshold: %d", dout);
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// Morphic scalar update (amplitude = 10)
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#20;
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we = 1;
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addr = 10'd0;
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update_enable = 1;
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morphic_amplitude = 32'sd10; // Amplitude = 10
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#20;
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we = 0;
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update_enable = 0;
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// Read back updated threshold
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#20;
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addr = 10'd0;
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#20;
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$display("Updated threshold: %d", dout);
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// Pattern match lookup
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#20;
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pattern_addr = 10'd0;
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#20;
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$display("Pattern match threshold: %d", pattern_match_threshold);
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#100;
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$finish;
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end
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endmodule
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