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https://github.com/allaunthefox/Research-Stack.git
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- Prover-Integrated Orchestration Layers (L0-L3): Goedel-Prover-V2 watchdog, BFS-Prover-V2 swarm consensus, bf4prover topology adaptation - FAMM Verilator benchmark: uniform vs preshaped delay comparison (4.4x speedup) - Swarm topological device prober: 11 agents probing traces, caps, delays, errors, vias, PDN - Spec sheet puller: 10 components with key params and topological relevance - Virtual FPGA system tests: 6/6 passed, 134K ops/s throughput - Fixed merge conflicts in AI-Newton test_experiment.ipynb
87 lines
3.4 KiB
Bash
87 lines
3.4 KiB
Bash
#!/usr/bin/env bash
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set -euo pipefail
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TOP="dvi_texel_transmitter"
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DEVICE="GW1NR-LV9QN88PC6/I5"
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FAMILY="GW1N-9C"
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CST="tangnano9k_dvi.cst"
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# Constraint file for DVI texel transmitter
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cat > "$CST" << 'CSTEOF'
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// Tang Nano 9K DVI Texel Transmitter constraints
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// HDMI connector pin mappings for GW1NR-LV9QN88PC6/I5
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IO_LOC "clk_27mhz" 52;
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IO_PORT "clk_27mhz" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
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IO_LOC "rst_n" 4;
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IO_PORT "rst_n" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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// DVI/HDMI output pins (TMDS-compatible, 3.3V LVCMOS output)
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// Tang Nano 9K HDMI connector uses direct FPGA pin routing
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// DVI_R[7:0]
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IO_LOC "dvi_r[7]" 30; IO_PORT "dvi_r[7]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_r[6]" 31; IO_PORT "dvi_r[6]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_r[5]" 34; IO_PORT "dvi_r[5]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_r[4]" 35; IO_PORT "dvi_r[4]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_r[3]" 36; IO_PORT "dvi_r[3]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_r[2]" 37; IO_PORT "dvi_r[2]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_r[1]" 38; IO_PORT "dvi_r[1]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_r[0]" 39; IO_PORT "dvi_r[0]" IO_TYPE=LVCMOS33 DRIVE=8;
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// DVI_G[7:0]
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IO_LOC "dvi_g[7]" 41; IO_PORT "dvi_g[7]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_g[6]" 42; IO_PORT "dvi_g[6]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_g[5]" 43; IO_PORT "dvi_g[5]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_g[4]" 44; IO_PORT "dvi_g[4]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_g[3]" 45; IO_PORT "dvi_g[3]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_g[2]" 46; IO_PORT "dvi_g[2]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_g[1]" 56; IO_PORT "dvi_g[1]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_g[0]" 57; IO_PORT "dvi_g[0]" IO_TYPE=LVCMOS33 DRIVE=8;
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// DVI_B[7:0]
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IO_LOC "dvi_b[7]" 58; IO_PORT "dvi_b[7]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_b[6]" 60; IO_PORT "dvi_b[6]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_b[5]" 61; IO_PORT "dvi_b[5]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_b[4]" 62; IO_PORT "dvi_b[4]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_b[3]" 63; IO_PORT "dvi_b[3]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_b[2]" 64; IO_PORT "dvi_b[2]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_b[1]" 65; IO_PORT "dvi_b[1]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_b[0]" 66; IO_PORT "dvi_b[0]" IO_TYPE=LVCMOS33 DRIVE=8;
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// DVI sync and clock
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IO_LOC "dvi_hsync" 67; IO_PORT "dvi_hsync" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_vsync" 68; IO_PORT "dvi_vsync" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_de" 69; IO_PORT "dvi_de" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "dvi_clk" 70; IO_PORT "dvi_clk" IO_TYPE=LVCMOS33 DRIVE=8;
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// LEDs
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IO_LOC "led[0]" 10; IO_LOC "led[1]" 11; IO_LOC "led[2]" 13;
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IO_LOC "led[3]" 14; IO_LOC "led[4]" 15; IO_LOC "led[5]" 16;
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IO_PORT "led[0]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_PORT "led[1]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_PORT "led[2]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_PORT "led[3]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_PORT "led[4]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_PORT "led[5]" IO_TYPE=LVCMOS33 DRIVE=8;
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CSTEOF
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JSON="${TOP}.json"
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PNR="${TOP}_pnr.json"
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FS="${TOP}.fs"
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echo "=== DVI Texel Transmitter Build ==="
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echo "Synth: ${TOP}.v"
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yosys -p "read_verilog ${TOP}.v; synth_gowin -top ${TOP} -json ${JSON}; stat" 2>&1 | tail -15
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echo "Place & Route..."
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nextpnr-himbaechel --device "${DEVICE}" --json "${JSON}" --write "${PNR}" \
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--vopt "family=${FAMILY}" --vopt "cst=${CST}" \
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--chipdb /usr/share/nextpnr/himbaechel/gowin/chipdb-${FAMILY}.bin 2>&1 | tail -10
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echo "Bitstream..."
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gowin_pack -d "${FAMILY}" -o "${FS}" "${PNR}" 2>&1
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echo "=== ${FS} ==="
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ls -lh "${FS}"
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