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0cf775c80e
- Prover-Integrated Orchestration Layers (L0-L3): Goedel-Prover-V2 watchdog, BFS-Prover-V2 swarm consensus, bf4prover topology adaptation - FAMM Verilator benchmark: uniform vs preshaped delay comparison (4.4x speedup) - Swarm topological device prober: 11 agents probing traces, caps, delays, errors, vias, PDN - Spec sheet puller: 10 components with key params and topological relevance - Virtual FPGA system tests: 6/6 passed, 134K ops/s throughput - Fixed merge conflicts in AI-Newton test_experiment.ipynb
218 lines
8 KiB
Verilog
218 lines
8 KiB
Verilog
// Tang Nano 9K DVI/HDMI Texel Transmitter
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// Target: Gowin GW1NR-LV9QN88PC6/I5 (QN88), 27 MHz onboard oscillator
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//
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// Generates 640×480@60Hz DVI-compatible video with texel-encoded pixels.
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// Each pixel is a NUVMAP texel: R = φ(k), G = mass(t), B = chiral state.
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//
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// Timing: 640×480 @ 60Hz = 25.175 MHz pixel clock.
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// The Gowin PLL generates 25.175 MHz from the 27 MHz reference.
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`timescale 1ns / 1ps
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module dvi_texel_transmitter (
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input clk_27mhz, // Pin 52, 27 MHz onboard oscillator
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input rst_n, // Pin 4, active-low reset
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// DVI/HDMI digital output (connector pins)
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output [7:0] dvi_r,
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output [7:0] dvi_g,
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output [7:0] dvi_b,
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output dvi_hsync,
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output dvi_vsync,
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output dvi_de,
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output dvi_clk,
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// Debug: onboard LEDs
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output [5:0] led
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);
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//══════════════════════════════════════════════════════════════════════
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// PLL: 27 MHz → 25.175 MHz (640×480 @ 60Hz pixel clock)
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// Gowin rPLL primitive
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//══════════════════════════════════════════════════════════════════════
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wire clk_pixel;
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wire pll_lock;
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rPLL #(
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.FCLKIN("27"),
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.DYN_IDIV_SEL("false"),
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.IDIV_SEL(3), // Fref = 27/3 = 9 MHz
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.DYN_FBDIV_SEL("false"),
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.FBDIV_SEL(14), // Fvco = 9 * 14 = 126 MHz
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.DYN_ODIV_SEL("false"),
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.ODIV_SEL(5), // Fout = 126/5 = 25.2 MHz (~25.175, 0.1% error)
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.PSDA_SEL("0000"),
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.DYN_DA_EN("false"),
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.DUTYDA_SEL("1000"),
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.CLKOUT_FT_DIR(1'b1),
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.CLKOUTP_FT_DIR(1'b1),
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.CLKOUT_DLY_STEP(0),
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.CLKOUTP_DLY_STEP(0),
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.CLKFB_SEL("internal"),
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.CLKOUT_BYPASS("false"),
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.CLKOUTP_BYPASS("false"),
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.CLKOUTD_BYPASS("false"),
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.DYN_SDIV_SEL(2),
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.CLKOUTD_SRC("CLKOUT"),
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.CLKOUTD3_SRC("CLKOUT"),
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.DEVICE("GW1N-9C")
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) pll_inst (
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.CLKOUT(clk_pixel),
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.LOCK(pll_lock),
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.CLKOUTP(),
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.CLKOUTD(),
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.CLKOUTD3(),
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.RESET(~rst_n),
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.RESET_P(),
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.CLKIN(clk_27mhz),
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.CLKFB(1'b0),
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.FBDSEL({6{1'b0}}),
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.IDSEL({6{1'b0}}),
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.ODSEL({6{1'b0}}),
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.PSDA({4{1'b0}}),
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.DUTYDA({4{1'b0}}),
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.FDLY({4{1'b0}})
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);
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//══════════════════════════════════════════════════════════════════════
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// VGA/DVI Timing: 640×480 @ 60Hz
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// Standard VESA timing parameters (in pixel clocks)
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//══════════════════════════════════════════════════════════════════════
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localparam H_ACTIVE = 640;
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localparam H_FRONT = 16;
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localparam H_SYNC = 96;
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localparam H_BACK = 48;
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localparam H_TOTAL = H_ACTIVE + H_FRONT + H_SYNC + H_BACK; // 800
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localparam V_ACTIVE = 480;
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localparam V_FRONT = 10;
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localparam V_SYNC = 2;
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localparam V_BACK = 33;
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localparam V_TOTAL = V_ACTIVE + V_FRONT + V_SYNC + V_BACK; // 525
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// Counters
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reg [10:0] h_count;
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reg [10:0] v_count;
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reg hsync, vsync, de;
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always @(posedge clk_pixel or negedge rst_n) begin
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if (!rst_n) begin
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h_count <= 0;
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v_count <= 0;
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end else begin
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if (h_count < H_TOTAL - 1) begin
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h_count <= h_count + 1;
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end else begin
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h_count <= 0;
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if (v_count < V_TOTAL - 1)
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v_count <= v_count + 1;
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else
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v_count <= 0;
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end
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end
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end
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always @(posedge clk_pixel) begin
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hsync <= (h_count >= H_ACTIVE + H_FRONT) &&
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(h_count < H_ACTIVE + H_FRONT + H_SYNC);
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vsync <= (v_count >= V_ACTIVE + V_FRONT) &&
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(v_count < V_ACTIVE + V_FRONT + V_SYNC);
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de <= (h_count < H_ACTIVE) && (v_count < V_ACTIVE);
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end
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assign dvi_hsync = hsync;
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assign dvi_vsync = vsync;
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assign dvi_de = de;
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//══════════════════════════════════════════════════════════════════════
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// Texel Pattern Generator
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//
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// Each pixel (x, y) encodes three NUVMAP texel parameters:
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// R[7:0] = φ-phase (soliton φ-parameter, 0–255)
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// G[7:0] = mass(t) (PIST shell mass, 0–255)
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// B[7:0] = chiral state (0=achiral, 1=left, 2=right, 3=scarred)
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//
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// 480 rows × 640 columns = 307,200 texels per frame
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// At 60 fps = 18,432,000 texels/second
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//
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// The texel map is generated from a simple function over (x, y):
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// texel(x, y) = PIST(k = x % 16, t = y % 32)
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// φ = k * 16 (shell index, 0–240)
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// mass = t*(2k+1-t) (hyperbolic paraboloid)
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// chiral = ((mass > 64) ? 1 : 0) | ((mass > 128) ? 2 : 0)
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//══════════════════════════════════════════════════════════════════════
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reg [7:0] r_val, g_val, b_val;
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wire [7:0] k, t;
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wire [11:0] mass_raw;
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// PIST coordinate from pixel position
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assign k = h_count[3:0]; // x mod 16 → shell index
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assign t = v_count[4:0]; // y mod 32 → offset in shell
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// PIST mass: m = t * (2k + 1 - t)
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// t ranges 0–31, 2k+1 ranges 1–31
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// Maximum mass: 15.5 * 15.5 ≈ 240 (fits in 12 bits)
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assign mass_raw = t * (({4'b0, k, 1'b0}) + 1 - t); // t * (2k+1-t)
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wire [7:0] k_scaled;
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assign k_scaled = {k, 4'b0000}; // k * 16 → 0–240
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always @(posedge clk_pixel) begin
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// R = shell index (φ-phase), scaled 0–240
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r_val <= k_scaled;
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// G = PIST mass, scaled to 0–255
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g_val <= mass_raw[11:4]; // ÷16 for visual range
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// B = chiral state encoding
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if (mass_raw > 128 && k > 7)
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b_val <= 8'hE0; // chiral_scarred (pink)
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else if (k > 8)
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b_val <= 8'h3F; // right_handed_vector_bias (cyan)
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else if (mass_raw > 64)
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b_val <= 8'hFF; // left_handed_mass_bias (bright blue)
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else
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b_val <= 8'h1F; // achiral_stable (very dim blue)
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end
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always @(posedge clk_pixel) begin
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if (de) begin
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dvi_r <= r_val;
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dvi_g <= g_val;
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dvi_b <= b_val;
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end else begin
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dvi_r <= 8'h00;
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dvi_g <= 8'h00;
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dvi_b <= 8'h00;
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end
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end
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assign dvi_clk = clk_pixel;
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//══════════════════════════════════════════════════════════════════════
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// LED indicators (active low)
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// led[0] = PLL locked
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// led[1] = VSYNC
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// led[2] = DE active
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// led[3] = mass > 128 (scarred pixel)
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// led[4] = mass == 0 (shell boundary)
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// led[5] = frame counter LSB
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//══════════════════════════════════════════════════════════════════════
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reg [23:0] frame_count;
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always @(posedge clk_pixel or negedge rst_n) begin
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if (!rst_n) frame_count <= 0;
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else if (vsync && v_count == V_ACTIVE + V_FRONT) frame_count <= frame_count + 1;
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end
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assign led[0] = ~pll_lock;
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assign led[1] = ~vsync;
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assign led[2] = ~de;
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assign led[3] = ~(mass_raw > 128);
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assign led[4] = ~(mass_raw == 0);
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assign led[5] = ~frame_count[0];
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endmodule
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