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42 lines
1.3 KiB
Verilog
42 lines
1.3 KiB
Verilog
// Hutter/metaprobe symbol substitution core for Tang Nano 9K surface tests.
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//
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// This is intentionally small: one input byte becomes a 4-bit dictionary code
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// plus a hit flag. The host owns full codec/search logic; FPGA owns the
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// deterministic substitution witness path.
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`timescale 1ns / 1ps
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module hutter_symbol_substitution_core (
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input wire [7:0] symbol,
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output reg [3:0] code,
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output reg hit
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);
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always @* begin
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hit = 1'b1;
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code = 4'h0;
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case (symbol)
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8'h20: code = 4'h0; // space
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"e", "E": code = 4'h1;
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"t", "T": code = 4'h2;
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"a", "A": code = 4'h3;
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"o", "O": code = 4'h4;
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"i", "I": code = 4'h5;
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"n", "N": code = 4'h6;
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"s", "S": code = 4'h7;
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"r", "R": code = 4'h8;
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"h", "H": code = 4'h9;
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"l", "L": code = 4'hA;
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"d": code = 4'hB;
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"c", "C": code = 4'hC;
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"u", "U": code = 4'hD;
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"F": code = 4'hE; // full metaprobe token marker
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"D": code = 4'hF; // delta metaprobe token marker
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default: begin
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hit = 1'b0;
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code = symbol[3:0];
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end
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endcase
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end
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endmodule
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