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09f2f3044a
research_stack_top.fs (2.0MB) — all modules synthesized: - Blitter6502OISC (4K memory, SUBTLEQ CPU) - q16_lut_core (Q16_16 arithmetic, 8 ops) - blitter_memory_map (8-bit ↔ 32-bit bridge) - voltage_mode_controller (4 BRAM modes) - scale_space_bram (Gaussian kernel banks) - highs_pivot_accelerator (simplex pipeline) Timing: 195.92 MHz (PASS at 27 MHz target, 7.2x margin) Device: GW1NR-LV9QN88PC6/I5 (Tang Nano 9K) To flash: openFPGALoader -b tangnano9k research_stack_top.fs
36 lines
885 B
Text
36 lines
885 B
Text
// Research Stack Tang Nano 9K Constraint File
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// Board: Sipeed Tang Nano 9K
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// FPGA: Gowin GW1NR-LV9QN88PC6/I5
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IO_LOC "clk" 52;
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IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
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IO_LOC "rst_n" 4;
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IO_PORT "rst_n" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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IO_LOC "user_btn" 3;
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IO_PORT "user_btn" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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IO_LOC "led[0]" 10;
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IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[1]" 11;
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IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[2]" 13;
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IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[3]" 14;
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IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[4]" 15;
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IO_PORT "led[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[5]" 16;
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IO_PORT "led[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "uart_tx" 17;
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IO_PORT "uart_tx" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
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IO_LOC "uart_rx" 18;
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IO_PORT "uart_rx" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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