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https://github.com/allaunthefox/Research-Stack.git
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53e38e4c71
Pipeline: - q16_lut_vcn.py: Q16_16 LUT generation + VCN frame encoding (8 ops) - braid_vcn_encoder.py: Delta+RLE → RS ECC → ChaCha20 → VCN → MKV - braid_search.py: Sidon set slots, soliton search, QUBO optimization - test_braid_pipeline.py: 67 tests covering full round-trip WebGPU/Scripts: - braid_fft.wgsl: Cooley-Tukey radix-2 FFT on phase vectors - reed_solomon_vcn.py: Reed-Solomon ECC for VCN frame data - chacha20_braid.py: ChaCha20 encryption + key derivation - polynomial_commitment.py: KZG scheme for receipt verification Lean: - BraidBitwiseODE.lean: XOR crossing, O(1) integration, 2 proved theorems FPGA (Tang Nano 9K): - q16_lut_core.v: 8-op arithmetic, 2-stage pipeline, BRAM reciprocal - braid_crossing_core.v: 4-stage crossing residual, 7 Q16 instances - Testbenches with edge cases + VCD dumps
232 lines
8.1 KiB
Verilog
232 lines
8.1 KiB
Verilog
// ============================================================================
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// braid_crossing_core.v - Braid Crossing Residual Computation
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// Target: Tang Nano 9K (GW1NR-9)
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// Pipeline: 4 stages
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// Stage 1: Input latch + strand decomposition
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// Stage 2: Q16_16 arithmetic operations via q16_lut_core
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// Stage 3: Crossing residual accumulation
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// Stage 4: Output register + done flag
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// ============================================================================
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// Strand format: 128 bits = 4 x Q16_16 values
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// strand[127:96] = x0 (head position x)
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// strand[ 95:64] = y0 (head position y)
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// strand[ 63:32] = x1 (tail position x)
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// strand[ 31: 0] = y1 (tail position y)
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//
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// Crossing residual = cross product of direction vectors
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// residual = (x1_a - x0_a)*(y1_b - y0_b) - (y1_a - y0_a)*(x1_b - x0_b)
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// ============================================================================
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module braid_crossing_core (
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input wire clk,
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input wire rst,
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input wire start,
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input wire [127:0] strand_a,
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input wire [127:0] strand_b,
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output reg [127:0] result,
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output reg done
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);
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// ----------------------------------------------------------------
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// Strand decomposition
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// ----------------------------------------------------------------
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// Strand A components (Q16.16)
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wire [31:0] ax0 = strand_a[127:96];
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wire [31:0] ay0 = strand_a[95:64];
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wire [31:0] ax1 = strand_a[63:32];
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wire [31:0] ay1 = strand_a[31:0];
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// Strand B components (Q16.16)
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wire [31:0] bx0 = strand_b[127:96];
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wire [31:0] by0 = strand_b[95:64];
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wire [31:0] bx1 = strand_b[63:32];
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wire [31:0] by1 = strand_b[31:0];
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// ----------------------------------------------------------------
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// Q16_16 LUT core instances for arithmetic
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// We need 4 subtractions and 2 multiplications + 1 subtraction
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// ----------------------------------------------------------------
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// Stage 2 arithmetic: compute direction vectors
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// dx_a = ax1 - ax0, dy_a = ay1 - ay0
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// dx_b = bx1 - bx0, dy_b = by1 - by0
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wire [31:0] sub_dx_a_result, sub_dy_a_result;
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wire [31:0] sub_dx_b_result, sub_dy_b_result;
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wire sub_dx_a_valid, sub_dy_a_valid;
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wire sub_dx_b_valid, sub_dy_b_valid;
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// Subtraction units for direction vectors
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reg sub_start;
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reg [15:0] sub_a_dx_a, sub_b_dx_a;
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reg [15:0] sub_a_dy_a, sub_b_dy_a;
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reg [15:0] sub_a_dx_b, sub_b_dx_b;
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reg [15:0] sub_a_dy_b, sub_b_dy_b;
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q16_lut_core u_sub_dx_a (
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.clk(clk), .rst(rst),
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.op_select(3'd1), // sub
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.a(sub_a_dx_a), .b(sub_b_dx_a),
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.result(sub_dx_a_result), .valid(sub_dx_a_valid)
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);
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q16_lut_core u_sub_dy_a (
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.clk(clk), .rst(rst),
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.op_select(3'd1), // sub
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.a(sub_a_dy_a), .b(sub_b_dy_a),
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.result(sub_dy_a_result), .valid(sub_dy_a_valid)
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);
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q16_lut_core u_sub_dx_b (
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.clk(clk), .rst(rst),
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.op_select(3'd1), // sub
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.a(sub_a_dx_b), .b(sub_b_dx_b),
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.result(sub_dx_b_result), .valid(sub_dx_b_valid)
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);
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q16_lut_core u_sub_dy_b (
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.clk(clk), .rst(rst),
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.op_select(3'd1), // sub
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.a(sub_a_dy_b), .b(sub_b_dy_b),
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.result(sub_dy_b_result), .valid(sub_dy_b_valid)
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);
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// Stage 3 arithmetic: compute cross products
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// cross1 = dx_a * dy_b
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// cross2 = dy_a * dx_b
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// residual = cross1 - cross2
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reg [15:0] mul_a1, mul_b1;
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reg [15:0] mul_a2, mul_b2;
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wire [31:0] mul1_result, mul2_result;
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wire mul1_valid, mul2_valid;
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q16_lut_core u_mul1 (
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.clk(clk), .rst(rst),
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.op_select(3'd2), // mul
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.a(mul_a1), .b(mul_b1),
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.result(mul1_result), .valid(mul1_valid)
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);
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q16_lut_core u_mul2 (
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.clk(clk), .rst(rst),
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.op_select(3'd2), // mul
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.a(mul_a2), .b(mul_b2),
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.result(mul2_result), .valid(mul2_valid)
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);
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reg [15:0] sub_final_a, sub_final_b;
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wire [31:0] residual_result;
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wire residual_valid;
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q16_lut_core u_sub_final (
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.clk(clk), .rst(rst),
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.op_select(3'd1), // sub
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.a(sub_final_a), .b(sub_final_b),
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.result(residual_result), .valid(residual_valid)
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);
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// ----------------------------------------------------------------
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// Pipeline control
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// ----------------------------------------------------------------
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reg [3:0] pipe_valid;
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reg computing;
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always @(posedge clk) begin
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if (rst) begin
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pipe_valid <= 4'b0000;
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computing <= 1'b0;
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end else begin
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// Shift pipeline valid bits
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pipe_valid <= {pipe_valid[2:0], start & ~computing};
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if (start && !computing) begin
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computing <= 1'b1;
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end
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// Clear computing when done emerges
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if (pipe_valid[3]) begin
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computing <= 1'b0;
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end
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end
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end
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// ----------------------------------------------------------------
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// Stage 1: Input latch + decompose into 16-bit operands
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// ----------------------------------------------------------------
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always @(posedge clk) begin
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if (rst) begin
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sub_a_dx_a <= 16'd0; sub_b_dx_a <= 16'd0;
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sub_a_dy_a <= 16'd0; sub_b_dy_a <= 16'd0;
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sub_a_dx_b <= 16'd0; sub_b_dx_b <= 16'd0;
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sub_a_dy_b <= 16'd0; sub_b_dy_b <= 16'd0;
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end else if (start && !computing) begin
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// Feed 16-bit halves of Q16_16 values into subtractors
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// Use lower 16 bits of each Q16_16 component
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sub_a_dx_a <= ax1[15:0]; sub_b_dx_a <= ax0[15:0];
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sub_a_dy_a <= ay1[15:0]; sub_b_dy_a <= ay0[15:0];
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sub_a_dx_b <= bx1[15:0]; sub_b_dx_b <= bx0[15:0];
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sub_a_dy_b <= by1[15:0]; sub_b_dy_b <= by0[15:0];
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end
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end
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// ----------------------------------------------------------------
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// Stage 2: Latch direction vectors, feed to multipliers
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// ----------------------------------------------------------------
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reg [31:0] dx_a_reg, dy_a_reg, dx_b_reg, dy_b_reg;
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always @(posedge clk) begin
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if (rst) begin
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dx_a_reg <= 32'd0; dy_a_reg <= 32'd0;
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dx_b_reg <= 32'd0; dy_b_reg <= 32'd0;
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mul_a1 <= 16'd0; mul_b1 <= 16'd0;
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mul_a2 <= 16'd0; mul_b2 <= 16'd0;
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end else begin
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dx_a_reg <= sub_dx_a_result;
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dy_a_reg <= sub_dy_a_result;
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dx_b_reg <= sub_dx_b_result;
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dy_b_reg <= sub_dy_b_result;
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// Feed to multipliers: cross1 = dx_a * dy_b, cross2 = dy_a * dx_b
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mul_a1 <= sub_dx_a_result[15:0]; mul_b1 <= sub_dy_b_result[15:0];
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mul_a2 <= sub_dy_a_result[15:0]; mul_b2 <= sub_dx_b_result[15:0];
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end
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end
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// ----------------------------------------------------------------
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// Stage 3: Latch cross products, feed to final subtractor
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// ----------------------------------------------------------------
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always @(posedge clk) begin
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if (rst) begin
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sub_final_a <= 16'd0;
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sub_final_b <= 16'd0;
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end else begin
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sub_final_a <= mul1_result[15:0];
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sub_final_b <= mul2_result[15:0];
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end
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end
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// ----------------------------------------------------------------
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// Stage 4: Output register + done flag
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// ----------------------------------------------------------------
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always @(posedge clk) begin
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if (rst) begin
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result <= 128'd0;
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done <= 1'b0;
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end else begin
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done <= pipe_valid[3];
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if (pipe_valid[3]) begin
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// Pack residual into result:
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// [127:96] = residual (Q16.16 crossing value)
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// [95:64] = dx_a (direction A x)
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// [63:32] = dy_b (direction B y)
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// [31:0] = sign-extended residual (for downstream use)
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result <= {
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residual_result,
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dx_a_reg,
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dy_b_reg,
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{16'd0, residual_result[15:0]}
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};
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end
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end
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end
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endmodule
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