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https://github.com/allaunthefox/Research-Stack.git
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09f2f3044a
research_stack_top.fs (2.0MB) — all modules synthesized: - Blitter6502OISC (4K memory, SUBTLEQ CPU) - q16_lut_core (Q16_16 arithmetic, 8 ops) - blitter_memory_map (8-bit ↔ 32-bit bridge) - voltage_mode_controller (4 BRAM modes) - scale_space_bram (Gaussian kernel banks) - highs_pivot_accelerator (simplex pipeline) Timing: 195.92 MHz (PASS at 27 MHz target, 7.2x margin) Device: GW1NR-LV9QN88PC6/I5 (Tang Nano 9K) To flash: openFPGALoader -b tangnano9k research_stack_top.fs
41 lines
929 B
Bash
Executable file
41 lines
929 B
Bash
Executable file
#!/usr/bin/env bash
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set -euo pipefail
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cd "$(dirname "$0")"
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TOP="research_stack_top"
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CST="research_stack_tangnano9k.cst"
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JSON="research_stack_top.json"
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PNR="research_stack_top_pnr.json"
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FS="research_stack_top.fs"
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DEVICE="GW1NR-LV9QN88PC6/I5"
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FAMILY="GW1N-9C"
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FREQ=27
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Q16_V="../../5-Applications/out/verilog/q16_lut_core.v"
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echo "=== Synthesis ==="
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yosys -p "
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read_verilog -sv \
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${Q16_V} \
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blitter_memory_map.v \
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voltage_mode_controller.v \
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scale_space_bram.v \
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highs_pivot_accelerator.v \
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Blitter6502OISC_small.v \
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research_stack_top.v;
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synth_gowin -top ${TOP} -json ${JSON};
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stat
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"
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echo ""
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echo "=== Place & Route ==="
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nextpnr-himbaechel --device "${DEVICE}" --json "${JSON}" --write "${PNR}" \
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--freq "${FREQ}" --vopt "family=${FAMILY}" --vopt "cst=${CST}"
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echo ""
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echo "=== Bitstream ==="
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gowin_pack -d "${FAMILY}" -o "${FS}" "${PNR}"
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echo ""
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echo "=== Done: ${FS} ==="
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ls -lh "${FS}"
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