Research-Stack/4-Infrastructure/hardware/build_cff_scanner.sh
Brandon Schneider 0cf775c80e collapse: prover orchestration layers, FAMM verilator harness, swarm topological prober, spec sheets, virtual FPGA system tests, merge conflict resolution
- Prover-Integrated Orchestration Layers (L0-L3): Goedel-Prover-V2 watchdog, BFS-Prover-V2 swarm consensus, bf4prover topology adaptation
- FAMM Verilator benchmark: uniform vs preshaped delay comparison (4.4x speedup)
- Swarm topological device prober: 11 agents probing traces, caps, delays, errors, vias, PDN
- Spec sheet puller: 10 components with key params and topological relevance
- Virtual FPGA system tests: 6/6 passed, 134K ops/s throughput
- Fixed merge conflicts in AI-Newton test_experiment.ipynb
2026-05-06 23:42:01 -05:00

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Bash

#!/usr/bin/env bash
set -euo pipefail
TOP="cff_invariant_scanner"
DEVICE="GW1NR-LV9QN88PC6/I5"
FAMILY="GW1N-9C"
FREQ_MHZ="27"
CST="tangnano9k_uart_loopback.cst"
JSON="${TOP}.json"
PNR="${TOP}_pnr.json"
FS="${TOP}.fs"
echo "=== CFF Invariant Scanner Build ==="
RTL_FILES=("${TOP}.v" "uart_rx.v" "uart_tx.v")
echo "=== Synthesis (Yosys) ==="
yosys -p "read_verilog ${RTL_FILES[*]}; synth_gowin -top ${TOP} -json ${JSON}; stat" 2>&1 | tail -15
echo "=== Place & Route (nextpnr-himbaechel) ==="
nextpnr-himbaechel --device "${DEVICE}" --json "${JSON}" --write "${PNR}" \
--freq "${FREQ_MHZ}" --vopt "family=${FAMILY}" --vopt "cst=${CST}" \
--chipdb /usr/share/nextpnr/himbaechel/gowin/chipdb-${FAMILY}.bin 2>&1 | tail -15
echo "=== Bitstream (gowin_pack) ==="
gowin_pack -d "${FAMILY}" -o "${FS}" "${PNR}" 2>&1
echo "=== Build complete: ${FS} ==="
echo "sudo openFPGALoader -b tangnano9k -f ${FS}"