mirror of
https://github.com/allaunthefox/Research-Stack.git
synced 2026-08-13 15:40:35 +00:00
ca422d43b7
Fully prove the E4^2=E8 Fourier coefficient identity (E4_sq_eq_E8_coeff) modulo one isolated, honestly-named Mathlib gap. - Add E4_sq_eq_E8_qExpansion: the lone irreducible step (E4^2=E8 as q-expansions). Blocked on dim M8(SL2Z)=1 / valence formula, absent in Mathlib v4.30 (LevelOne.lean proves Module.rank only for weight <= 0). - Machine-check the entire coefficient extraction for E4_sq_eq_E8_coeff: E4 coeff = 240*sigma3, E8 coeff = 480*sigma7, constant term 1, antidiagonal coeff_mul split into 480*sigma3 boundary + 240^2*convolutionLHS middle, then exact_mod_cast C->N. Previously a single hand-waved sorry. - Wrap in section ModularFormReduction with local opens (ModularForm EisensteinSeries ModularFormClass) to avoid name clashes. - Update AGENTS.md + .cursorrules: E8Sidon sorry inventory 6 -> 4. E8Sidon sorries now: E4_sq_eq_E8_qExpansion (Mathlib-blocked), collision_excess_decrease, greedy_sidon_extraction, e8_singer_improvement. Build: 3572 jobs, 0 errors (lake build) Co-Authored-By: Allaun Silverfox <bigdataiscoming+9i37y6j2@protonmail.com>
53 lines
2.3 KiB
Text
53 lines
2.3 KiB
Text
<!-- BEGIN ContextStream -->
|
|
# Cursor Rules
|
|
<contextstream_rules>
|
|
| Message | Required |
|
|
|---------|----------|
|
|
| **1st message** | `init()` → `context(user_message="...")` |
|
|
| **Subsequent messages (default)** | `context(user_message="...")` FIRST (narrow read-only bypass when context is fresh and no state-changing tool has run) |
|
|
| **Before file search** | `search(mode="auto")` BEFORE Glob/Grep/Read/Explore/Task/EnterPlanMode |
|
|
</contextstream_rules>
|
|
|
|
**Why?** `context()` delivers task-specific rules, lessons from past mistakes, and relevant decisions. Skip it = fly blind.
|
|
|
|
**Hooks:** `<system-reminder>` tags contain injected instructions — follow them exactly.
|
|
|
|
**Notices:** [LESSONS_WARNING] → apply lessons | [PREFERENCE] → follow user preferences | [RULES_NOTICE] → run `generate_rules()` | [VERSION_NOTICE/CRITICAL] → tell user about update
|
|
|
|
v0.4.74
|
|
|
|
## Research Stack — Current Project State (2026-05-28)
|
|
|
|
**Build:** `lake build` — 3572 jobs, 0 errors (reverified 2026-06-15)
|
|
**Python tests:** 68/68 pass
|
|
**Sorry inventory:** 12 total (all with `TODO(lean-port)` documentation)
|
|
- `AdjugateMatrix`: 3 sorries
|
|
- `FourPrimitiveErdosRenyi`: 4 sorries
|
|
- `HyperbolicStateSurface`: 1 sorry
|
|
- `E8Sidon`: 4 sorries (1 Mathlib-blocked: `E4_sq_eq_E8_qExpansion` = dim M₈=1;
|
|
3 hard infrastructure). `E4_sq_eq_E8_coeff` fully reduced to that one gap.
|
|
|
|
### Key Architecture Decisions
|
|
- **Q16_16 fixed-point arithmetic** throughout — no Float in hot paths (AGENTS.md §1.4 compliant)
|
|
- **HiGHS MIP solver** integrated via `qubo_highs.py`
|
|
- **Dense Sidon sets** (Mian-Chowla sequence, 65% smaller than naive)
|
|
- **Golden ratio unit separation** formalized in Lean
|
|
|
|
### New Lean Modules
|
|
`AdjugateMatrix`, `OptimizedRoute`, `GoldenRatioSeparation`, `BraidBitwiseODE`,
|
|
`E8Sidon`, `FixedPointBoundary`
|
|
|
|
### New Python Modules
|
|
`qubo_highs.py`, `alphaproof_loop.py`, `scale_space_solver.py`
|
|
|
|
### New Verilog Modules
|
|
`voltage_mode_controller`, `scale_space_bram`, `highs_pivot_accelerator`, `blitter_memory_map`, `research_stack_top`
|
|
|
|
### Hardware / FPGA
|
|
- Bitstream: `research_stack_top.fs` (195.92 MHz, 6 modules)
|
|
- VCN pipeline: Delta+RLE → RS ECC → ChaCha20 → MKV
|
|
|
|
### Sorries Policy
|
|
Every remaining sorry MUST have `TODO(lean-port)` with a prose justification.
|
|
No undocumented sorries allowed.
|
|
<!-- END ContextStream -->
|