Research-Stack/4-Infrastructure/hardware/sparkle/generated/sparkle_phi_s3c_payload.sv

// Generated by Sparkle HDL
// Module: sparkle_phi_s3c_payload

module sparkle_phi_s3c_payload (
    input logic clk,
    input logic rst,
    input logic user_btn,
    input logic i2s_sd,
    output logic [5:0] led,
    output logic uart_tx,
    output logic i2s_sclk,
    output logic i2s_ws,
    output logic [15:0] handleK
);

    logic [3:0] state_next;
    logic [3:0] state_q;
    logic [3:0] manual_state_next;
    logic [3:0] manual_state_q;
    logic audio_mode_next;
    logic audio_mode_q;
    logic [3:0] audio_state;
    logic button_d1;
    logic button_d2;
    logic [18:0] debounce_cnt_next;
    logic [18:0] debounce_cnt_q;
    logic button_debounced;
    logic button_debounced_prev;
    logic button_rise;
    logic [24:0] tick_next;
    logic [24:0] tick_q;
    logic tick_wrap;
    logic [15:0] phase_next;
    logic [15:0] phase_q;
    logic emit_w;
    logic uart_event;
    logic uart_start;
    logic uart_baud_done;
    logic uart_last_bit;
    logic uart_busy_next;
    logic uart_busy_q;
    logic [7:0] uart_baud_inc;
    logic [7:0] uart_baud_next;
    logic [7:0] uart_baud_q;
    logic [3:0] uart_bit_inc;
    logic [3:0] uart_bit_next;
    logic [3:0] uart_bit_q;
    logic [3:0] uart_frame_tag_load;
    logic [3:0] uart_frame_payload_load;
    logic [9:0] uart_frame_load;
    logic uart_byte_idx_next;
    logic uart_byte_idx_q;
    logic uart_all_done;
    logic [9:0] uart_shift_step;
    logic [9:0] uart_shift_next;
    logic [9:0] uart_shift_q;
    logic [2:0] sclk_div_next;
    logic [2:0] sclk_div_q;
    logic [5:0] ws_div_next;
    logic [5:0] ws_div_q;
    logic i2s_sclk_prev;
    logic i2s_sclk_rise;
    logic i2s_ws_prev;
    logic i2s_ws_q;
    logic i2s_ws_edge;
    logic i2s_ws_rise;
    logic [4:0] i2s_bit_cnt_next;
    logic [4:0] i2s_bit_cnt_q;
    logic i2s_shift_en;
    logic [23:0] i2s_shift_next;
    logic [23:0] i2s_shift_q;
    logic [23:0] i2s_sample_next;
    logic [23:0] i2s_sample_q;


    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            button_d1 <= 1'd0;
        else
            button_d1 <= user_btn;
    end

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            button_d2 <= 1'd0;
        else
            button_d2 <= button_d1;
    end

    assign debounce_cnt_next = (button_d2 ? ((debounce_cnt_q == 19'd500000) ? 19'd500000 : (debounce_cnt_q + 19'd1)) : 19'd0);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            debounce_cnt_q <= 19'd0;
        else
            debounce_cnt_q <= debounce_cnt_next;
    end

    assign button_debounced = (debounce_cnt_q == 19'd500000);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            button_debounced_prev <= 1'd0;
        else
            button_debounced_prev <= button_debounced;
    end

    assign button_rise = (button_debounced & ~button_debounced_prev);

    assign tick_next = (tick_q + 25'd1);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            tick_q <= 25'd0;
        else
            tick_q <= tick_next;
    end

    assign tick_wrap = (tick_q == 25'd0);

    assign manual_state_next = (button_rise ? (manual_state_q + 4'd1) : manual_state_q);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            manual_state_q <= 4'd0;
        else
            manual_state_q <= manual_state_next;
    end

    assign audio_mode_next = (button_rise ? ~audio_mode_q : audio_mode_q);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            audio_mode_q <= 1'd0;
        else
            audio_mode_q <= audio_mode_next;
    end

    assign sclk_div_next = (sclk_div_q + 3'd1);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            sclk_div_q <= 3'd0;
        else
            sclk_div_q <= sclk_div_next;
    end

    assign i2s_sclk = sclk_div_q[2:2];

    assign ws_div_next = (i2s_sclk_rise ? (ws_div_q + 6'd1) : ws_div_q);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            ws_div_q <= 6'd0;
        else
            ws_div_q <= ws_div_next;
    end

    assign i2s_ws_q = ws_div_q[5:5];

    assign i2s_ws = i2s_ws_q;

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            i2s_sclk_prev <= 1'd0;
        else
            i2s_sclk_prev <= i2s_sclk;
    end

    assign i2s_sclk_rise = (i2s_sclk & ~i2s_sclk_prev);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            i2s_ws_prev <= 1'd0;
        else
            i2s_ws_prev <= i2s_ws_q;
    end

    assign i2s_ws_edge = ~(i2s_ws_q == i2s_ws_prev);

    assign i2s_ws_rise = (i2s_ws_q & ~i2s_ws_prev);

    assign i2s_bit_cnt_next = (i2s_ws_edge ? 5'd0 : (i2s_sclk_rise ? (i2s_bit_cnt_q + 5'd1) : i2s_bit_cnt_q));

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            i2s_bit_cnt_q <= 5'd0;
        else
            i2s_bit_cnt_q <= i2s_bit_cnt_next;
    end

    assign i2s_shift_en = (i2s_sclk_rise & ((i2s_bit_cnt_q > 5'd0) & (i2s_bit_cnt_q < 5'd25)));

    assign i2s_shift_next = (i2s_ws_edge ? i2s_shift_q : (i2s_shift_en ? {i2s_shift_q[22:0], i2s_sd} : i2s_shift_q));

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            i2s_shift_q <= 24'd0;
        else
            i2s_shift_q <= i2s_shift_next;
    end

    assign i2s_sample_next = (i2s_ws_rise ? i2s_shift_q : i2s_sample_q);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            i2s_sample_q <= 24'd0;
        else
            i2s_sample_q <= i2s_sample_next;
    end

    assign audio_state = i2s_sample_q[22:19];

    assign state_next = (audio_mode_q ? (tick_wrap ? audio_state : state_q) : manual_state_next);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            state_q <= 4'd0;
        else
            state_q <= state_next;
    end

    assign phase_next = (tick_wrap ? (phase_q + 16'd40503) : phase_q);

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            phase_q <= 16'd0;
        else
            phase_q <= phase_next;
    end

    assign emit_w = ((state_q == 4'd0) ? 1'd0 : ((state_q == 4'd1) ? 1'd1 : ((state_q == 4'd2) ? 1'd0 : ((state_q == 4'd3) ? 1'd0 : ((state_q == 4'd4) ? 1'd1 : ((state_q == 4'd5) ? 1'd1 : ((state_q == 4'd6) ? 1'd1 : ((state_q == 4'd7) ? 1'd0 : ((state_q == 4'd8) ? 1'd0 : ((state_q == 4'd9) ? 1'd1 : ((state_q == 4'd10) ? 1'd1 : ((state_q == 4'd11) ? 1'd1 : ((state_q == 4'd12) ? 1'd1 : ((state_q == 4'd13) ? 1'd1 : ((state_q == 4'd14) ? 1'd0 : ((state_q == 4'd15) ? 1'd0 : 1'd0))))))))))))))));

    assign handleK = ((state_q == 4'd0) ? 16'd1 : ((state_q == 4'd1) ? 16'd1 : ((state_q == 4'd2) ? 16'd1 : ((state_q == 4'd3) ? 16'd2 : ((state_q == 4'd4) ? 16'd2 : ((state_q == 4'd5) ? 16'd2 : ((state_q == 4'd6) ? 16'd2 : ((state_q == 4'd7) ? 16'd2 : ((state_q == 4'd8) ? 16'd3 : ((state_q == 4'd9) ? 16'd3 : ((state_q == 4'd10) ? 16'd3 : ((state_q == 4'd11) ? 16'd3 : ((state_q == 4'd12) ? 16'd3 : ((state_q == 4'd13) ? 16'd3 : ((state_q == 4'd14) ? 16'd3 : ((state_q == 4'd15) ? 16'd4 : 16'd1))))))))))))))));

    assign led = {tick_q[24:24], audio_mode_q, emit_w, state_q[2:0]};

    assign uart_event = (button_rise | tick_wrap);

    assign uart_start = (uart_event & ~uart_busy_q);

    assign uart_baud_done = (uart_baud_q == 8'd233);

    assign uart_last_bit = (uart_bit_q == 4'd9);

    assign uart_all_done = (uart_last_bit & uart_byte_idx_q);

    assign uart_byte_idx_next = (uart_start ? 1'd0 : ((uart_busy_q & (uart_baud_done & uart_last_bit)) ? (uart_all_done ? 1'd0 : 1'd1) : uart_byte_idx_q));

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            uart_byte_idx_q <= 1'd0;
        else
            uart_byte_idx_q <= uart_byte_idx_next;
    end

    assign uart_busy_next = (uart_start ? 1'd1 : ((uart_busy_q & (uart_baud_done & uart_last_bit)) ? (uart_all_done ? 1'd0 : 1'd1) : uart_busy_q));

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            uart_busy_q <= 1'd0;
        else
            uart_busy_q <= uart_busy_next;
    end

    assign uart_baud_inc = (uart_baud_q + 8'd1);

    assign uart_baud_next = (uart_start ? 8'd0 : (uart_busy_q ? (uart_baud_done ? 8'd0 : uart_baud_inc) : 8'd0));

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            uart_baud_q <= 8'd0;
        else
            uart_baud_q <= uart_baud_next;
    end

    assign uart_bit_inc = (uart_bit_q + 4'd1);

    assign uart_bit_next = (uart_start ? 4'd0 : ((uart_busy_q & uart_baud_done) ? (uart_last_bit ? 4'd0 : uart_bit_inc) : uart_bit_q));

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            uart_bit_q <= 4'd0;
        else
            uart_bit_q <= uart_bit_next;
    end

    assign uart_frame_tag_load = (uart_byte_idx_next ? 4'd6 : 4'd5);

    assign uart_frame_payload_load = (uart_byte_idx_next ? {audio_mode_q, emit_w, handleK[1:0]} : state_next);

    assign uart_frame_load = {1'd1, uart_frame_tag_load, uart_frame_payload_load, 1'd0};

    assign uart_shift_step = {1'd1, uart_shift_q[9:1]};

    assign uart_shift_next = (uart_start ? uart_frame_load : ((uart_busy_q & uart_baud_done) ? (uart_last_bit ? (uart_all_done ? uart_shift_step : uart_frame_load) : uart_shift_step) : uart_shift_q));

    always_ff @(posedge clk or posedge rst) begin
        if (rst)
            uart_shift_q <= 10'd1023;
        else
            uart_shift_q <= uart_shift_next;
    end

    assign uart_tx = (uart_busy_q ? uart_shift_q[0:0] : 1'd1);

endmodule