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46 lines
1.7 KiB
Verilog
46 lines
1.7 KiB
Verilog
// Sparkle Tang Nano 9K board wrapper
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// Target: Sipeed Tang Nano 9K, Gowin GW1NR-LV9QN88PC6/I5, QN88 package
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//
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// This wrapper exposes only real board-level pins. The payload is generated
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// from Sparkle IR by tools/lean/Semantics/GenerateSparklePhiS3C.lean.
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`timescale 1ns / 1ps
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module SparkleTangNano9KTop (
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input wire clk, // Pin 52, 27 MHz oscillator
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input wire rst_n, // Pin 4, active-low reset button
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input wire user_btn, // Pin 3, active-low user button on board
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output wire [5:0] led, // Pins 10,11,13,14,15,16
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output wire uart_tx, // Pin 17, USB-UART TX from FPGA
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/* verilator lint_off UNUSEDSIGNAL */
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input wire uart_rx, // Pin 18, USB-UART RX to FPGA (unused by payload)
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/* verilator lint_on UNUSEDSIGNAL */
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// External I2S microphone/header pins. SPH0645-style mics are I2S, not PDM.
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// The FPGA generates master clocks (SCLK + WS); the mic drives SD.
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output wire i2s_sclk,
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output wire i2s_ws,
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input wire i2s_sd
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);
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// Tang Nano 9K buttons are active-low. Internal payloads use active-high
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// edge detection for user button, so invert it here.
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wire user_btn_pressed = ~user_btn;
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wire rst = ~rst_n;
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/* verilator lint_off UNUSEDSIGNAL */
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wire [15:0] handleK; // driven by payload for UART frame, not routed to pins
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/* verilator lint_on UNUSEDSIGNAL */
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sparkle_phi_s3c_payload payload (
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.clk(clk),
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.rst(rst),
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.user_btn(user_btn_pressed),
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.i2s_sd(i2s_sd),
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.led(led),
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.uart_tx(uart_tx),
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.i2s_sclk(i2s_sclk),
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.i2s_ws(i2s_ws),
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.handleK(handleK)
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);
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endmodule
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