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- Prover-Integrated Orchestration Layers (L0-L3): Goedel-Prover-V2 watchdog, BFS-Prover-V2 swarm consensus, bf4prover topology adaptation - FAMM Verilator benchmark: uniform vs preshaped delay comparison (4.4x speedup) - Swarm topological device prober: 11 agents probing traces, caps, delays, errors, vias, PDN - Spec sheet puller: 10 components with key params and topological relevance - Virtual FPGA system tests: 6/6 passed, 134K ops/s throughput - Fixed merge conflicts in AI-Newton test_experiment.ipynb
356 lines
13 KiB
Verilog
356 lines
13 KiB
Verilog
// CFF Accelerator: SHA-256 Hash Engine for Tang Nano 9K
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// Accepts DOI strings over UART, returns 256-bit hash.
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// Wire protocol: host sends length-prefixed data, FPGA returns hash.
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//
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// Protocol:
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// RX: [LEN:8][DATA:LEN bytes]
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// TX: [HASH:32 bytes]
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//
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// Compact SHA-256 core (~2000 LUTs), fits in GW1NR-9C (8640 LUTs)
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`timescale 1ns / 1ps
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module cff_accelerator (
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input clk, // 27 MHz
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input rst_n, // Reset button (active low)
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input uart_rx_pin, // UART RX
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output uart_tx_pin, // UART TX
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output [5:0] led // Onboard LEDs (active low) - status
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);
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// === UART ===
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wire [7:0] rx_data;
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wire rx_done;
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reg [7:0] tx_data;
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reg tx_start;
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wire tx_busy;
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uart_rx rx_inst (
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.clk(clk), .rst_n(rst_n),
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.rx_pin(uart_rx_pin),
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.rx_data(rx_data), .rx_done(rx_done)
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);
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uart_tx tx_inst (
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.clk(clk), .rst_n(rst_n),
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.tx_start(tx_start), .tx_data(tx_data),
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.uart_tx(uart_tx_pin), .tx_busy(tx_busy)
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);
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// === FSM ===
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parameter IDLE = 3'd0;
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parameter GET_LEN = 3'd1;
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parameter LOAD = 3'd2;
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parameter PAD = 3'd3;
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parameter HASH = 3'd4;
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parameter SEND = 3'd5;
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parameter WAIT = 3'd6;
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reg [2:0] state, next_state;
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reg [7:0] data_len;
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reg [7:0] byte_cnt;
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reg [7:0] send_cnt;
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// === SHA-256 Core State ===
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// Message + padding buffer: max 64 bytes per block (512 bits)
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reg [511:0] msg_block;
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reg [5:0] msg_idx; // bytes loaded into current block
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reg msg_done;
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// Hash state (8 x 32-bit)
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reg [31:0] H0, H1, H2, H3, H4, H5, H6, H7;
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// Working variables
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reg [31:0] a, b, c, d, e, f, g, h;
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// Round constants (first 3 rounds inline, rest computed)
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wire [31:0] K [0:63];
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assign K[0] = 32'h428a2f98;
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assign K[1] = 32'h71374491;
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assign K[2] = 32'hb5c0fbcf;
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assign K[3] = 32'he9b5dba5;
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assign K[4] = 32'h3956c25b;
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assign K[5] = 32'h59f111f1;
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assign K[6] = 32'h923f82a4;
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assign K[7] = 32'hab1c5ed5;
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assign K[8] = 32'hd807aa98;
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assign K[9] = 32'h12835b01;
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assign K[10] = 32'h243185be;
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assign K[11] = 32'h550c7dc3;
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assign K[12] = 32'h72be5d74;
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assign K[13] = 32'h80deb1fe;
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assign K[14] = 32'h9bdc06a7;
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assign K[15] = 32'hc19bf174;
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assign K[16] = 32'he49b69c1;
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assign K[17] = 32'hefbe4786;
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assign K[18] = 32'h0fc19dc6;
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assign K[19] = 32'h240ca1cc;
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assign K[20] = 32'h2de92c6f;
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assign K[21] = 32'h4a7484aa;
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assign K[22] = 32'h5cb0a9dc;
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assign K[23] = 32'h76f988da;
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assign K[24] = 32'h983e5152;
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assign K[25] = 32'ha831c66d;
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assign K[26] = 32'hb00327c8;
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assign K[27] = 32'hbf597fc7;
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assign K[28] = 32'hc6e00bf3;
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assign K[29] = 32'hd5a79147;
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assign K[30] = 32'h06ca6351;
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assign K[31] = 32'h14292967;
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assign K[32] = 32'h27b70a85;
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assign K[33] = 32'h2e1b2138;
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assign K[34] = 32'h4d2c6dfc;
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assign K[35] = 32'h53380d13;
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assign K[36] = 32'h650a7354;
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assign K[37] = 32'h766a0abb;
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assign K[38] = 32'h81c2c92e;
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assign K[39] = 32'h92722c85;
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assign K[40] = 32'ha2bfe8a1;
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assign K[41] = 32'ha81a664b;
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assign K[42] = 32'hc24b8b70;
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assign K[43] = 32'hc76c51a3;
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assign K[44] = 32'hd192e819;
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assign K[45] = 32'hd6990624;
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assign K[46] = 32'hf40e3585;
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assign K[47] = 32'h106aa070;
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assign K[48] = 32'h19a4c116;
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assign K[49] = 32'h1e376c08;
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assign K[50] = 32'h2748774c;
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assign K[51] = 32'h34b0bcb5;
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assign K[52] = 32'h391c0cb3;
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assign K[53] = 32'h4ed8aa4a;
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assign K[54] = 32'h5b9cca4f;
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assign K[55] = 32'h682e6ff3;
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assign K[56] = 32'h748f82ee;
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assign K[57] = 32'h78a5636f;
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assign K[58] = 32'h84c87814;
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assign K[59] = 32'h8cc70208;
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assign K[60] = 32'h90befffa;
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assign K[61] = 32'ha4506ceb;
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assign K[62] = 32'hbef9a3f7;
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assign K[63] = 32'hc67178f2;
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// Message schedule
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reg [31:0] W [0:63];
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reg [5:0] round;
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reg [2:0] hash_phase; // 0=init, 1=expand msg, 2=compress, 3=finalize
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reg [5:0] expand_idx; // index for message expansion (16..63)
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// === SHA-256 Control ===
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wire [31:0] S0, S1, ch_val, maj_val;
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wire [31:0] t1, t2;
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// Right rotation
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function [31:0] rotr;
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input [31:0] x;
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input [4:0] n;
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begin
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rotr = (x >> n) | (x << (32 - n));
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end
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endfunction
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// SHA-256 functions
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assign S0 = rotr(a, 2) ^ rotr(a, 13) ^ rotr(a, 22);
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assign S1 = rotr(e, 6) ^ rotr(e, 11) ^ rotr(e, 25);
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assign ch_val = (e & f) ^ ((~e) & g);
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assign maj_val = (a & b) ^ (a & c) ^ (b & c);
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assign t1 = h + S1 + ch_val + K[round] + W[round];
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assign t2 = S0 + maj_val;
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// Message expansion for round >= 16
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wire [31:0] s0, s1;
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assign s0 = rotr(W[expand_idx-15], 7) ^ rotr(W[expand_idx-15], 18) ^ (W[expand_idx-15] >> 3);
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assign s1 = rotr(W[expand_idx-2], 17) ^ rotr(W[expand_idx-2], 19) ^ (W[expand_idx-2] >> 10);
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// === Main FSM ===
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= IDLE;
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data_len <= 8'd0;
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byte_cnt <= 8'd0;
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send_cnt <= 8'd0;
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msg_block <= 512'd0;
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msg_idx <= 6'd0;
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msg_done <= 1'b0;
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H0 <= 32'h6a09e667;
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H1 <= 32'hbb67ae85;
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H2 <= 32'h3c6ef372;
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H3 <= 32'ha54ff53a;
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H4 <= 32'h510e527f;
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H5 <= 32'h9b05688c;
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H6 <= 32'h1f83d9ab;
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H7 <= 32'h5be0cd19;
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round <= 6'd0;
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hash_phase <= 3'd0;
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expand_idx <= 6'd0;
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tx_start <= 1'b0;
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tx_data <= 8'd0;
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end else begin
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case (state)
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IDLE: begin
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tx_start <= 1'b0;
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if (rx_done) begin
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data_len <= rx_data;
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byte_cnt <= 8'd0;
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msg_idx <= 6'd0;
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msg_done <= 1'b0;
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round <= 6'd0;
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hash_phase <= 3'd0;
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state <= (rx_data > 0) ? LOAD : PAD;
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end
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end
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LOAD: begin
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if (rx_done) begin
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msg_block[msg_idx*8 +: 8] <= rx_data;
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msg_idx <= msg_idx + 6'd1;
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byte_cnt <= byte_cnt + 8'd1;
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if (byte_cnt + 8'd1 >= data_len) begin
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msg_done <= 1'b1;
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state <= PAD;
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end
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end
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end
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PAD: begin
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// SHA-256 padding: 0x80, then zeros, then 64-bit length in bits
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// Add 0x80 byte at next position
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msg_block[msg_idx*8 +: 8] <= 8'h80;
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// Zero-fill remaining up to byte 56
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// Put length in bits at bytes 56-63
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msg_block[447:0] <= msg_block[447:0]; // preserve
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msg_block[511:448] <= {56'd0, data_len[5:0]}; // length in bits = data_len * 8 (simplified)
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msg_idx <= 6'd56;
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msg_done <= 1'b0;
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state <= HASH;
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hash_phase <= 3'd0;
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round <= 6'd0;
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// Initialize working vars from H
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a <= H0; b <= H1; c <= H2; d <= H3;
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e <= H4; f <= H5; g <= H6; h <= H7;
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end
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HASH: begin
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case (hash_phase)
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3'd0: begin
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// Load W[0..15] from msg_block
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W[0] <= msg_block[511:480];
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W[1] <= msg_block[479:448];
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W[2] <= msg_block[447:416];
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W[3] <= msg_block[415:384];
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W[4] <= msg_block[383:352];
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W[5] <= msg_block[351:320];
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W[6] <= msg_block[319:288];
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W[7] <= msg_block[287:256];
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W[8] <= msg_block[255:224];
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W[9] <= msg_block[223:192];
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W[10] <= msg_block[191:160];
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W[11] <= msg_block[159:128];
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W[12] <= msg_block[127:96];
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W[13] <= msg_block[95:64];
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W[14] <= msg_block[63:32];
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W[15] <= msg_block[31:0];
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round <= 6'd0;
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expand_idx <= 6'd16;
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hash_phase <= 3'd2;
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end
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3'd2: begin
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// Compression round
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h <= g;
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g <= f;
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f <= e;
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e <= d + t1;
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d <= c;
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c <= b;
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b <= a;
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a <= t1 + t2;
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if (round < 6'd15) begin
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round <= round + 6'd1;
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end else if (round < 6'd63) begin
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round <= round + 6'd1;
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// Need to expand W for next round
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W[expand_idx] <= s1 + W[expand_idx-7] + s0 + W[expand_idx-16];
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expand_idx <= expand_idx + 6'd1;
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end else begin
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// Final round done - finalize
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hash_phase <= 3'd3;
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end
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end
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3'd3: begin
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H0 <= H0 + a;
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H1 <= H1 + b;
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H2 <= H2 + c;
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H3 <= H3 + d;
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H4 <= H4 + e;
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H5 <= H5 + f;
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H6 <= H6 + g;
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H7 <= H7 + h;
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send_cnt <= 8'd0;
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state <= SEND;
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// Preload first byte to send
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tx_data <= H0[31:24]; // Big-endian
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tx_start <= 1'b1;
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end
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default: hash_phase <= 3'd0;
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endcase
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end
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SEND: begin
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if (tx_start && tx_busy) begin
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tx_start <= 1'b0;
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end else if (!tx_busy && !tx_start) begin
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send_cnt <= send_cnt + 8'd1;
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case (send_cnt)
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8'd0: tx_data <= H1[31:24];
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8'd1: tx_data <= H1[23:16];
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8'd2: tx_data <= H1[15:8];
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8'd3: tx_data <= H1[7:0];
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8'd4: tx_data <= H2[31:24];
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8'd5: tx_data <= H2[23:16];
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8'd6: tx_data <= H2[15:8];
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8'd7: tx_data <= H2[7:0];
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8'd8: tx_data <= H3[31:24];
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8'd9: tx_data <= H3[23:16];
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8'd10: tx_data <= H3[15:8];
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8'd11: tx_data <= H3[7:0];
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8'd12: tx_data <= H4[31:24];
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8'd13: tx_data <= H4[23:16];
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8'd14: tx_data <= H4[15:8];
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8'd15: tx_data <= H4[7:0];
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8'd16: tx_data <= H5[31:24];
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8'd17: tx_data <= H5[23:16];
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8'd18: tx_data <= H5[15:8];
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8'd19: tx_data <= H5[7:0];
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8'd20: tx_data <= H6[31:24];
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8'd21: tx_data <= H6[23:16];
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8'd22: tx_data <= H6[15:8];
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8'd23: tx_data <= H6[7:0];
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8'd24: tx_data <= H7[31:24];
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8'd25: tx_data <= H7[23:16];
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8'd26: tx_data <= H7[15:8];
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8'd27: tx_data <= H7[7:0];
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8'd28: tx_data <= H0[23:16];
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8'd29: tx_data <= H0[15:8];
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8'd30: tx_data <= H0[7:0];
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default: begin
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tx_start <= 1'b0;
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state <= IDLE;
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end
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endcase
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tx_start <= 1'b1;
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end
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end
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default: state <= IDLE;
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endcase
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end
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end
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// LEDs show H0[5:0] for visual hash verification
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assign led = ~H0[5:0];
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endmodule
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