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534 lines
20 KiB
Verilog
534 lines
20 KiB
Verilog
// Morphic Scalar FPGA with S3C Manifold Integration
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// Derived from Lean: Semantics/S3C.lean + Semantics/MorphicScalar.lean
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// Target: Gowin GW1NR-9 (Tang Nano 9K)
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// Q16.16 fixed-point arithmetic with S3C genus-3 manifold processing
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// Corrections per expansion paths document: I2S (not PDM) for SPH0645
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`timescale 1ns / 1ps
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// ═══════════════════════════════════════════════════════════════════════════
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// Scalar State Encoding (4-bit state ID)
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// ═══════════════════════════════════════════════════════════════════════════
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localparam STATE_SUPERPOSED = 4'd0;
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localparam STATE_SCOUTING = 4'd1;
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localparam STATE_MEASURE_LOCAL_NEED = 4'd2;
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localparam STATE_COLLAPSED_PROFILE = 4'd3;
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localparam STATE_EXECUTE = 4'd4;
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localparam STATE_RECEIPT = 4'd5;
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localparam STATE_AMPLITUDE_UPDATE = 4'd6;
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localparam STATE_QUERY_COLLECTIVE = 4'd7;
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localparam STATE_COLLECTIVE_RESPONSE = 4'd8;
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localparam STATE_QUERY_LLM = 4'd9;
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localparam STATE_DIRECTED = 4'd10;
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localparam STATE_HOLD = 4'd11;
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localparam STATE_OPERATOR_ALERT = 4'd12;
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localparam STATE_LOW_POWER_PASSIVE = 4'd13;
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localparam STATE_QUARANTINE = 4'd14;
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localparam STATE_MIGRATE = 4'd15;
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// ═══════════════════════════════════════════════════════════════════════════
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// S3C Shell Decomposition: n = k^2 + a
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// ═══════════════════════════════════════════════════════════════════════════
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module s3c_shell_decomposition (
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input wire [15:0] n, // Input sample (unsigned 16-bit)
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output reg [15:0] k, // Shell index (coarse handle)
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output reg [15:0] a, // Lower offset (medium handle)
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output reg [15:0] b, // Upper offset (fine handle)
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output reg [31:0] mass, // Intersection form a*b
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output reg [15:0] width // Shell width = 2k+1 = a+b+1
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);
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// Compute k = floor(sqrt(n)) using binary search
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reg [15:0] sqrt_result;
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reg [15:0] sqrt_low;
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reg [15:0] sqrt_high;
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reg [15:0] sqrt_mid;
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reg [31:0] sqrt_sq;
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integer i;
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always @(*) begin
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sqrt_low = 0;
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sqrt_high = 16'd256;
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sqrt_result = 0;
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for (i = 0; i < 8; i = i + 1) begin
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sqrt_mid = (sqrt_low + sqrt_high) >> 1;
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sqrt_sq = sqrt_mid * sqrt_mid;
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if (sqrt_sq < n) begin
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sqrt_low = sqrt_mid + 1;
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end else begin
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sqrt_high = sqrt_mid;
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end
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end
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sqrt_result = sqrt_low - 1;
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if (sqrt_result > 255) sqrt_result = 255;
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end
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// Compute k, a, b, mass, width
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reg [31:0] k_sq;
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reg [31:0] k1_sq;
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always @(*) begin
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k = sqrt_result;
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k_sq = k * k;
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a = n - k_sq[15:0];
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k1_sq = (k + 1) * (k + 1);
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b = k1_sq[15:0] - n;
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mass = a * b;
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width = a + b + 1;
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end
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// S3C 3-Point Contact Detection
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// ═══════════════════════════════════════════════════════════════════════════
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module s3c_three_point_contact (
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input wire [15:0] handleK,
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input wire [15:0] handleA,
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input wire [15:0] handleB,
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output wire kappaA,
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output wire kappaB,
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output wire kappaC
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);
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assign kappaA = (handleA > 0);
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assign kappaB = (handleK > 0);
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assign kappaC = (handleB > 0);
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// S3C J-Score Calculation
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// J(n) = ab*F_m + (a-b)*F_p + <chi, F_c>
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// ═══════════════════════════════════════════════════════════════════════════
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module s3c_j_score (
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input wire [15:0] handleK,
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input wire [15:0] handleA,
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input wire [15:0] handleB,
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output wire [31:0] massResonance,
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output wire [31:0] mirrorResonance,
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output wire [31:0] spectralCoupling,
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output wire [31:0] total
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);
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wire [31:0] ab;
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wire [15:0] a_minus_b;
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wire [31:0] abs_a_minus_b;
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assign ab = handleA * handleB;
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assign a_minus_b = (handleA >= handleB) ? (handleA - handleB) : (handleB - handleA);
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assign abs_a_minus_b = {16'b0, a_minus_b};
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assign massResonance = ab;
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assign mirrorResonance = abs_a_minus_b;
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assign spectralCoupling = {16'b0, handleK};
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assign total = massResonance + mirrorResonance + spectralCoupling;
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// S3C Emission Gate
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// ═══════════════════════════════════════════════════════════════════════════
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module s3c_emission_gate (
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input wire kappaA,
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input wire kappaC,
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input wire [31:0] jScore,
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output wire emit
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);
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assign emit = kappaA && kappaC && (jScore > 0);
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// S3C Audio Processing Pipeline (Integrated with Morphic Scalar)
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// ═══════════════════════════════════════════════════════════════════════════
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module s3c_morphic_processor (
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input wire clk,
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input wire rst_n,
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input wire [15:0] audio_sample, // Unsigned 16-bit audio sample (from I2S)
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output reg [3:0] scalar_state,
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output reg s3c_emit,
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output reg [31:0] s3c_j_score,
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output reg [31:0] s3c_mass,
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output reg [15:0] handleK,
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output reg [15:0] handleA,
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output reg [15:0] handleB
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);
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// Pipeline Stage 1: Shell decomposition
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wire [15:0] k_stage1, a_stage1, b_stage1;
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wire [31:0] mass_stage1;
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wire [15:0] width_stage1;
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reg [15:0] k_stage1_reg, a_stage1_reg, b_stage1_reg;
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reg [31:0] mass_stage1_reg;
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s3c_shell_decomposition shell_inst (
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.n(audio_sample),
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.k(k_stage1),
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.a(a_stage1),
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.b(b_stage1),
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.mass(mass_stage1),
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.width(width_stage1)
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);
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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k_stage1_reg <= 16'd0;
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a_stage1_reg <= 16'd0;
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b_stage1_reg <= 16'd0;
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mass_stage1_reg <= 32'd0;
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end else begin
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k_stage1_reg <= k_stage1;
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a_stage1_reg <= a_stage1;
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b_stage1_reg <= b_stage1;
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mass_stage1_reg <= mass_stage1;
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end
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end
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// Pipeline Stage 2: Contact detection + J-score
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wire kappaA_stage2, kappaB_stage2, kappaC_stage2;
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wire [31:0] massResonance_stage2, mirrorResonance_stage2, spectralCoupling_stage2, jScore_stage2;
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reg kappaA_stage2_reg, kappaC_stage2_reg;
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reg [31:0] jScore_stage2_reg;
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reg [31:0] massResonance_stage2_reg;
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s3c_three_point_contact contact_inst (
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.handleK(k_stage1_reg),
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.handleA(a_stage1_reg),
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.handleB(b_stage1_reg),
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.kappaA(kappaA_stage2),
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.kappaB(kappaB_stage2),
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.kappaC(kappaC_stage2)
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);
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s3c_j_score jscore_inst (
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.handleK(k_stage1_reg),
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.handleA(a_stage1_reg),
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.handleB(b_stage1_reg),
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.massResonance(massResonance_stage2),
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.mirrorResonance(mirrorResonance_stage2),
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.spectralCoupling(spectralCoupling_stage2),
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.total(jScore_stage2)
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);
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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kappaA_stage2_reg <= 1'b0;
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kappaC_stage2_reg <= 1'b0;
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jScore_stage2_reg <= 32'd0;
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massResonance_stage2_reg <= 32'd0;
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end else begin
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kappaA_stage2_reg <= kappaA_stage2;
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kappaC_stage2_reg <= kappaC_stage2;
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jScore_stage2_reg <= jScore_stage2;
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massResonance_stage2_reg <= massResonance_stage2;
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end
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end
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// Pipeline Stage 3: Emission gate + State mapping
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wire emit_stage3;
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s3c_emission_gate emission_inst (
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.kappaA(kappaA_stage2_reg),
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.kappaC(kappaC_stage2_reg),
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.jScore(jScore_stage2_reg),
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.emit(emit_stage3)
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);
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// Map S3C emission to morphic scalar state
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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scalar_state <= STATE_SUPERPOSED;
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s3c_emit <= 1'b0;
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s3c_j_score <= 32'd0;
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s3c_mass <= 32'd0;
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handleK <= 16'd0;
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handleA <= 16'd0;
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handleB <= 16'd0;
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end else begin
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// S3C emit triggers state transition
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if (emit_stage3) begin
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scalar_state <= STATE_EXECUTE;
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end else begin
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scalar_state <= STATE_SUPERPOSED;
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end
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s3c_emit <= emit_stage3;
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s3c_j_score <= jScore_stage2_reg;
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s3c_mass <= massResonance_stage2_reg;
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handleK <= k_stage1_reg;
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handleA <= a_stage1_reg;
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handleB <= b_stage1_reg;
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end
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end
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// I2S Receiver for SPH0645 (Correction per expansion paths: I2S, not PDM)
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// ═══════════════════════════════════════════════════════════════════════════
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module i2s_receiver (
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input wire clk,
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input wire rst_n,
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input wire sclk, // I2S bit clock
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input wire ws, // Word select (LRCK)
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input wire sd, // Serial data
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output reg [15:0] left_sample,
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output reg [15:0] right_sample,
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output reg sample_valid
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);
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reg [3:0] bit_count;
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reg [15:0] shift_reg;
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reg ws_prev;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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bit_count <= 4'd0;
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shift_reg <= 16'd0;
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left_sample <= 16'd0;
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right_sample <= 16'd0;
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sample_valid <= 1'b0;
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ws_prev <= 1'b0;
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end else begin
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ws_prev <= ws;
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// Detect WS transition (start of new word)
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if (ws != ws_prev) begin
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bit_count <= 4'd0;
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sample_valid <= 1'b0;
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end
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// Sample on falling edge of SCLK (I2S standard)
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if (sclk == 1'b0) begin
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if (bit_count < 16) begin
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shift_reg <= {shift_reg[14:0], sd};
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bit_count <= bit_count + 1'b1;
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end else begin
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// Word complete
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if (ws_prev == 1'b0) begin
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left_sample <= {shift_reg[14:0], sd}; // MSB first
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end else begin
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right_sample <= {shift_reg[14:0], sd};
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sample_valid <= 1'b1;
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end
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end
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end
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end
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end
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// Top-Level: Morphic Scalar with S3C Integration
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// ═══════════════════════════════════════════════════════════════════════════
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module morphic_scalar_s3c_top (
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// Clock and reset
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input wire clk, // Pin 52 (27MHz)
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input wire rst_n, // Pin 4 (Reset_Button)
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// User input
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input wire user_btn, // Pin 3 (User_Button)
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// LED outputs
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output wire [5:0] led, // Pins 10,11,13,14,15,16
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// UART
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output wire uart_tx, // Pin 17
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input wire uart_rx, // Pin 18
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// I2S Microphone (SPH0645 - corrected per expansion paths)
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input wire i2s_sclk, // I2S bit clock
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input wire i2s_ws, // Word select (LRCK)
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input wire i2s_sd, // Serial data
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// State machine control
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input wire state_transition,
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input wire [3:0] target_state,
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input wire operator_available,
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// Outputs
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output reg [3:0] scalar_state,
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output reg s3c_emit,
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output reg [31:0] s3c_j_score,
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output reg [31:0] s3c_mass,
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output reg [15:0] handleK,
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output reg [15:0] handleA,
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output reg [15:0] handleB
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);
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// I2S receiver
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wire [15:0] left_sample, right_sample;
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wire sample_valid;
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i2s_receiver i2s_inst (
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.clk(clk),
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.rst_n(rst_n),
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.sclk(i2s_sclk),
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.ws(i2s_ws),
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.sd(i2s_sd),
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.left_sample(left_sample),
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.right_sample(right_sample),
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.sample_valid(sample_valid)
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);
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// Convert signed I2S to unsigned for S3C
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wire [15:0] audio_sample_unsigned;
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assign audio_sample_unsigned = left_sample + 16'sd8000;
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// S3C morphic processor
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s3c_morphic_processor s3c_inst (
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.clk(clk),
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.rst_n(rst_n),
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.audio_sample(audio_sample_unsigned),
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.scalar_state(scalar_state),
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.s3c_emit(s3c_emit),
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.s3c_j_score(s3c_j_score),
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.s3c_mass(s3c_mass),
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.handleK(handleK),
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.handleA(handleA),
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.handleB(handleB)
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);
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// LED status indicator
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wire pattern_match_detected;
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led_status_opt led_inst (
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.scalar_state(scalar_state),
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.s3c_emit(s3c_emit),
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.s3c_j_score(s3c_j_score),
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.pattern_match(pattern_match_detected),
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.led(led)
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);
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// UART debug output
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reg uart_tx_start;
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reg [7:0] uart_tx_data;
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wire uart_tx_busy;
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uart_tx_opt uart_inst (
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.clk(clk),
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.rst_n(rst_n),
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.tx_start(uart_tx_start),
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.tx_data(uart_tx_data),
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.uart_tx(uart_tx),
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.tx_busy(uart_tx_busy)
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);
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// Simple UART transmission for state monitoring
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reg [3:0] prev_state;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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prev_state <= 4'd0;
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uart_tx_start <= 1'b0;
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uart_tx_data <= 8'd0;
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end else begin
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if (scalar_state != prev_state && !uart_tx_busy) begin
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prev_state <= scalar_state;
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uart_tx_data <= {4'h5, scalar_state}; // state frame: high nibble tag + state
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uart_tx_start <= 1'b1;
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end else begin
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uart_tx_start <= 1'b0;
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end
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end
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end
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// User button integration
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reg user_btn_prev;
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wire user_btn_pressed = (user_btn && !user_btn_prev);
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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user_btn_prev <= 1'b0;
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end else begin
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user_btn_prev <= user_btn;
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end
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end
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// Override state transition when button pressed
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wire effective_state_transition = state_transition || user_btn_pressed;
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wire [3:0] effective_target_state = user_btn_pressed ? STATE_MEASURE_LOCAL_NEED : target_state;
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// LED Status Indicator Module
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// ═══════════════════════════════════════════════════════════════════════════
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module led_status_opt (
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input wire [3:0] scalar_state,
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input wire s3c_emit,
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input wire [31:0] s3c_j_score,
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input wire pattern_match,
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output reg [5:0] led
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);
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always @(*) begin
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led[5] = scalar_state[3];
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led[4] = scalar_state[2];
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led[3] = (s3c_j_score > 32'd1000); // High J-score threshold
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led[2] = s3c_emit;
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led[1] = (scalar_state == STATE_EXECUTE);
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led[0] = pattern_match;
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end
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endmodule
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// ═══════════════════════════════════════════════════════════════════════════
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// UART Debug Module (115200 baud @ 27MHz)
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// ═══════════════════════════════════════════════════════════════════════════
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module uart_tx_opt (
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input wire clk,
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input wire rst_n,
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input wire tx_start,
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input wire [7:0] tx_data,
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output reg uart_tx,
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output reg tx_busy
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);
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localparam BAUD_DIV = 16'd234;
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reg [15:0] baud_counter;
|
|
reg [2:0] bit_counter;
|
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reg [7:0] tx_shift;
|
|
reg [3:0] state;
|
|
|
|
always @(posedge clk or negedge rst_n) begin
|
|
if (!rst_n) begin
|
|
state <= 4'd0;
|
|
baud_counter <= 16'd0;
|
|
bit_counter <= 3'd0;
|
|
tx_shift <= 8'd0;
|
|
uart_tx <= 1'b1;
|
|
tx_busy <= 1'b0;
|
|
end else begin
|
|
case (state)
|
|
4'd0: begin
|
|
uart_tx <= 1'b1;
|
|
tx_busy <= 1'b0;
|
|
if (tx_start) begin
|
|
tx_shift <= tx_data;
|
|
bit_counter <= 3'd0;
|
|
baud_counter <= 16'd0;
|
|
state <= 4'd1;
|
|
tx_busy <= 1'b1;
|
|
end
|
|
end
|
|
4'd1: begin
|
|
uart_tx <= 1'b0;
|
|
if (baud_counter == BAUD_DIV) begin
|
|
baud_counter <= 16'd0;
|
|
state <= 4'd2;
|
|
end else begin
|
|
baud_counter <= baud_counter + 1'b1;
|
|
end
|
|
end
|
|
4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: begin
|
|
uart_tx <= tx_shift[bit_counter];
|
|
if (baud_counter == BAUD_DIV) begin
|
|
baud_counter <= 16'd0;
|
|
if (bit_counter == 3'd7) begin
|
|
state <= 4'd10;
|
|
end else begin
|
|
bit_counter <= bit_counter + 1'b1;
|
|
end
|
|
end else begin
|
|
baud_counter <= baud_counter + 1'b1;
|
|
end
|
|
end
|
|
4'd10: begin
|
|
uart_tx <= 1'b1;
|
|
if (baud_counter == BAUD_DIV) begin
|
|
state <= 4'd0;
|
|
end else begin
|
|
baud_counter <= baud_counter + 1'b1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
endmodule
|