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e5fb0a5f4d
Lean: update Semantics modules, add new numerics/physics data files Hardware: update FPGA bitstreams (tangnano9k_uart_loopback) Infra: k3s-flake tests, netcup-vps configuration, VCN compute substrate Docs: ARCHITECTURE, specs, citation updates
38 lines
1.1 KiB
Text
38 lines
1.1 KiB
Text
// Research Stack Unified Top-Level — Tang Nano 9K constraint file
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// Board: Sipeed Tang Nano 9K
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// FPGA: Gowin GW1NR-LV9QN88PC6/I5
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// Package: QN88
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// Clock: 27 MHz onboard oscillator
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//
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// Pin mapping matches SparkleTangNano9KTop / build_q16_lut conventions.
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// No I2S pins — this design uses UART + LEDs only.
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IO_LOC "clk" 52;
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IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
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IO_LOC "rst_n" 4;
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IO_PORT "rst_n" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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IO_LOC "user_btn" 3;
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IO_PORT "user_btn" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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// Six onboard LEDs: {cpu_busy, q16_done, voltage_mode[1:0], scale_select[1:0]}
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IO_LOC "led[0]" 10;
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IO_LOC "led[1]" 11;
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IO_LOC "led[2]" 13;
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IO_LOC "led[3]" 14;
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IO_LOC "led[4]" 15;
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IO_LOC "led[5]" 16;
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IO_PORT "led[0]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_PORT "led[1]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_PORT "led[2]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_PORT "led[3]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_PORT "led[4]" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_PORT "led[5]" IO_TYPE=LVCMOS33 DRIVE=8;
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// USB-UART via onboard BL702 bridge
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IO_LOC "uart_tx" 17;
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IO_PORT "uart_tx" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "uart_rx" 18;
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IO_PORT "uart_rx" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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