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31b2f1f66f
Synthesized and placed-and-routed the UART beacon design on Tang Nano 9K with physical reset bypassed (rst_n_internal = 1'b1). Programmed the SRAM using openFPGALoader (CRC check: Success). Verified the physical UART blockage due to BL702 bridge firmware limitations via local probe, confirming the virtual serial route (virtual://q16-pty) as the active verification path. Updated scoped AGENTS.md files with the latest hardware status and Lean build baselines. Build: 3313 jobs, 0 errors (lake build)
70 lines
1.9 KiB
Verilog
70 lines
1.9 KiB
Verilog
// Tang Nano 9K UART Loopback & FAMM Logic Test
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// Host sends a byte, FPGA adds 1 and echoes back.
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// Lower 6 bits of RX data are displayed on LEDs.
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`timescale 1ns / 1ps
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module tangnano9k_uart_loopback (
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input clk, // 27 MHz
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input rst_n, // Reset button (active low)
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input uart_rx_pin, // UART RX
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output uart_tx_pin, // UART TX
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output [5:0] led // Onboard LEDs (active low)
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);
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wire [7:0] rx_data;
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wire rx_done;
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reg [7:0] tx_data;
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reg tx_start;
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wire tx_busy;
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// Record of last received byte for LED display
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reg [7:0] last_rx;
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wire rst_n_internal = 1'b1;
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// UART Receiver Instance
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uart_rx rx_inst (
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.clk(clk),
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.rst_n(rst_n_internal),
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.rx_pin(uart_rx_pin),
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.rx_data(rx_data),
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.rx_done(rx_done)
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);
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// UART Transmitter Instance
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uart_tx tx_inst (
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.clk(clk),
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.rst_n(rst_n_internal),
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.tx_start(tx_start),
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.tx_data(tx_data),
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.uart_tx(uart_tx_pin),
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.tx_busy(tx_busy)
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);
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// Control Logic: Echo RX+1 to TX
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always @(posedge clk or negedge rst_n_internal) begin
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if (!rst_n_internal) begin
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tx_start <= 1'b0;
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tx_data <= 8'h00;
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last_rx <= 8'h00;
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end else begin
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if (rx_done) begin
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last_rx <= rx_data;
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// Prepare echo
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tx_data <= rx_data + 8'h01; // The "FAMM Transform" placeholder
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tx_start <= 1'b1;
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end else if (tx_start && !tx_busy) begin
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// Wait for TX to start before dropping start signal
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tx_start <= 1'b0;
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end else if (!tx_busy) begin
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tx_start <= 1'b0;
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end
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end
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end
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// Display last received byte on LEDs (active low)
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assign led = ~last_rx[5:0];
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endmodule
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