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aba1fba7ad
Security & correctness fixes from full adversarial review: Lean (7 fixes): - FixedPoint.lean: guard false theorem with n > 0 precondition - QFactor.lean: remove double-scaling error in energy decrease - AVMIsa/Step.lean: implement addSatQ16/subSatQ16 primitives - BraidEigensolid.lean: fix crossStep second output argument swap - SSMS.lean: complete ACI preservation proof (with rounding caveat) - HouseholderQR.lean: add n > 0 precondition to spectral theorem Verilog (7 fixes): - q16_lut_core.v: fix multiply shift (16 → 32 bits) - q16_lut_top.v: fix valid bit (0 → 1) - cff_accelerator.v: fix SHA-256 padding (len < 448 check) - research_stack_top.v: fix trigger aliasing (unique counters) - Blitter6502OISC_small.v: fix address width (15 → 16 bits) - spatial_hash_bram.v: add OOB write guard - tmr_oepi_safety_fsm.v: fix double-increment race WGSL (6 fixes): - shaders.wgsl: atomicAdd for concurrent writes - frustration_qubo.wgsl: double-buffer + CAS loop - braid_fft.wgsl: workgroupBarrier synchronization - burgers_scar_filter.wgsl: atomic E_bins array Rust (9 fixes): - thermodynamic.rs: Arc::from_raw → Arc::clone (double-free) - thermodynamic.rs: Box::into_raw → Box (leak) - tools/src/lib.rs: shell injection → shlex.quote - ene-node/src/lib.rs: LRU caps, constant-time HMAC, peer caps Python (6 fixes): - similarity/__init__.py: pickle.load → RestrictedUnpickler - AI-Feynman: torch.load → weights_only=True (14 calls) - fetch_arxiv.py, fetch_s2.py: eval → ast.literal_eval - topology.py: os.system → shutil.copy2 - SSH pipe: os.system → base64 pipe Build: lake build 3572 jobs, 0 errors
30 lines
797 B
Verilog
30 lines
797 B
Verilog
// Wrapper for q16_lut_core with separate valid output pin
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// FIX: Valid bit no longer overwrites MSB of result; widened output bus
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module q16_lut_top (
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input wire clk,
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input wire rst,
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input wire [2:0] op_select,
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input wire [15:0] a,
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input wire [15:0] b,
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output wire [31:0] result,
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output wire valid
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);
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wire [31:0] core_result;
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wire core_valid;
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q16_lut_core u_core (
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.clk (clk),
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.rst (rst),
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.op_select (op_select),
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.a (a),
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.b (b),
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.result (core_result),
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.valid (core_valid)
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);
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// FIX: Full 32-bit result preserved; valid exposed as separate pin
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assign result = core_result;
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assign valid = core_valid;
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endmodule
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