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31b2f1f66f
Synthesized and placed-and-routed the UART beacon design on Tang Nano 9K with physical reset bypassed (rst_n_internal = 1'b1). Programmed the SRAM using openFPGALoader (CRC check: Success). Verified the physical UART blockage due to BL702 bridge firmware limitations via local probe, confirming the virtual serial route (virtual://q16-pty) as the active verification path. Updated scoped AGENTS.md files with the latest hardware status and Lean build baselines. Build: 3313 jobs, 0 errors (lake build)
81 lines
2.2 KiB
Verilog
81 lines
2.2 KiB
Verilog
// Tang Nano 9K UART TX beacon.
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//
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// This isolates the fabric TX pin from RX framing and host protocol logic. It
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// emits a repeating receipt-like byte pattern at 115200 baud:
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// A6 42 51 31 36 0A
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// which reads as a board-level "Q16" beacon after the magic/version bytes.
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`timescale 1ns / 1ps
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module tangnano9k_uart_beacon (
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input clk,
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input rst_n,
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input uart_rx_pin,
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output uart_tx_pin,
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output [5:0] led
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);
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localparam GAP_CYCLES = 24'd2700000; // about 100 ms at 27 MHz
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wire tx_busy;
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reg tx_start;
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reg [7:0] tx_data;
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reg [23:0] gap_counter;
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reg [2:0] byte_index;
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reg [5:0] sent_count;
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wire rst_n_internal = 1'b1; // Bypass physical reset button
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uart_tx tx_inst (
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.clk(clk),
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.rst_n(rst_n_internal),
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.tx_start(tx_start),
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.tx_data(tx_data),
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.uart_tx(uart_tx_pin),
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.tx_busy(tx_busy)
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);
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function [7:0] beacon_byte;
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input [2:0] idx;
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begin
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case (idx)
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3'd0: beacon_byte = 8'hA6;
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3'd1: beacon_byte = 8'h42;
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3'd2: beacon_byte = 8'h51;
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3'd3: beacon_byte = 8'h31;
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3'd4: beacon_byte = 8'h36;
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default: beacon_byte = 8'h0A;
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endcase
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end
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endfunction
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always @(posedge clk or negedge rst_n_internal) begin
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if (!rst_n_internal) begin
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tx_start <= 1'b0;
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tx_data <= 8'h00;
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gap_counter <= 24'd0;
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byte_index <= 3'd0;
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sent_count <= 6'd0;
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end else begin
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tx_start <= 1'b0;
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if (gap_counter < GAP_CYCLES) begin
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gap_counter <= gap_counter + 24'd1;
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end else if (!tx_busy) begin
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tx_data <= beacon_byte(byte_index);
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tx_start <= 1'b1;
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sent_count <= sent_count + 6'd1;
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if (byte_index == 3'd5) begin
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byte_index <= 3'd0;
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gap_counter <= 24'd0;
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end else begin
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byte_index <= byte_index + 3'd1;
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end
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end
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end
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end
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assign led = ~sent_count;
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wire unused_rx = uart_rx_pin;
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wire unused_rst = rst_n;
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endmodule
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