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84 lines
2.6 KiB
Verilog
84 lines
2.6 KiB
Verilog
// UART Receiver for Tang Nano 9K
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// 115200 baud, 8N1 configuration
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// Clock: 27 MHz
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// Baud divider: 27MHz / 115200 ≈ 234
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`timescale 1ns / 1ps
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module uart_rx (
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input clk,
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input rst_n,
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input rx_pin,
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output [7:0] rx_data,
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output rx_done
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);
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localparam BAUD_DIV = 16'd234;
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localparam IDLE = 2'd0;
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localparam START = 2'd1;
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localparam DATA = 2'd2;
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localparam STOP = 2'd3;
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reg [15:0] baud_counter;
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reg [2:0] bit_counter;
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reg [1:0] state;
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reg [7:0] rx_shift;
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reg rx_done_r;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= IDLE;
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baud_counter <= 16'd0;
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bit_counter <= 3'd0;
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rx_shift <= 8'd0;
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rx_done_r <= 1'b0;
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end else begin
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rx_done_r <= 1'b0;
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case (state)
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IDLE: begin
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if (rx_pin == 1'b0) begin // Start bit detected
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state <= START;
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baud_counter <= 16'd0;
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end
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end
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START: begin
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if (baud_counter == BAUD_DIV / 2) begin // Sample in the middle
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if (rx_pin == 1'b0) begin
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state <= DATA;
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baud_counter <= 16'd0;
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bit_counter <= 3'd0;
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end else begin
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state <= IDLE;
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end
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end else begin
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baud_counter <= baud_counter + 1'b1;
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end
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end
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DATA: begin
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if (baud_counter == BAUD_DIV) begin
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rx_shift <= {rx_pin, rx_shift[7:1]};
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if (bit_counter == 3'd7) begin
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state <= STOP;
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end else begin
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bit_counter <= bit_counter + 1'b1;
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end
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baud_counter <= 16'd0;
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end else begin
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baud_counter <= baud_counter + 1'b1;
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end
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end
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STOP: begin
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if (baud_counter == BAUD_DIV) begin
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state <= IDLE;
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rx_done_r <= 1'b1;
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end else begin
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baud_counter <= baud_counter + 1'b1;
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end
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end
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endcase
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end
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end
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assign rx_data = rx_shift;
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assign rx_done = rx_done_r;
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endmodule
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