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https://github.com/allaunthefox/Research-Stack.git
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aba1fba7ad
Security & correctness fixes from full adversarial review: Lean (7 fixes): - FixedPoint.lean: guard false theorem with n > 0 precondition - QFactor.lean: remove double-scaling error in energy decrease - AVMIsa/Step.lean: implement addSatQ16/subSatQ16 primitives - BraidEigensolid.lean: fix crossStep second output argument swap - SSMS.lean: complete ACI preservation proof (with rounding caveat) - HouseholderQR.lean: add n > 0 precondition to spectral theorem Verilog (7 fixes): - q16_lut_core.v: fix multiply shift (16 → 32 bits) - q16_lut_top.v: fix valid bit (0 → 1) - cff_accelerator.v: fix SHA-256 padding (len < 448 check) - research_stack_top.v: fix trigger aliasing (unique counters) - Blitter6502OISC_small.v: fix address width (15 → 16 bits) - spatial_hash_bram.v: add OOB write guard - tmr_oepi_safety_fsm.v: fix double-increment race WGSL (6 fixes): - shaders.wgsl: atomicAdd for concurrent writes - frustration_qubo.wgsl: double-buffer + CAS loop - braid_fft.wgsl: workgroupBarrier synchronization - burgers_scar_filter.wgsl: atomic E_bins array Rust (9 fixes): - thermodynamic.rs: Arc::from_raw → Arc::clone (double-free) - thermodynamic.rs: Box::into_raw → Box (leak) - tools/src/lib.rs: shell injection → shlex.quote - ene-node/src/lib.rs: LRU caps, constant-time HMAC, peer caps Python (6 fixes): - similarity/__init__.py: pickle.load → RestrictedUnpickler - AI-Feynman: torch.load → weights_only=True (14 calls) - fetch_arxiv.py, fetch_s2.py: eval → ast.literal_eval - topology.py: os.system → shutil.copy2 - SSH pipe: os.system → base64 pipe Build: lake build 3572 jobs, 0 errors
320 lines
11 KiB
Verilog
320 lines
11 KiB
Verilog
// Research Stack Top-Level Module
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// Unified FPGA design for Tang Nano 9K (GW1NR-9C)
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// Combines: Blitter6502OISC + Q16 LUT + Memory Map + Voltage Controller
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// + Scale Space BRAM + HiGHS Pivot Accelerator
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// + Fractal Box Counter + FD Selector
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// + Spatial Hash BRAM + Density Selector
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`timescale 1ns / 1ps
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module research_stack_top (
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input wire clk, // 27 MHz oscillator (pin 52)
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input wire rst_n, // Active-low reset (pin 4)
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input wire user_btn, // Active-low user button (pin 3)
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output wire [5:0] led, // Status LEDs (pins 10,11,13,14,15,16)
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output wire uart_tx, // UART TX (pin 17)
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input wire uart_rx // UART RX (pin 18, unused)
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);
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// ── Reset & Button ─────────────────────────────────────────────
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wire rst = ~rst_n;
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wire btn_pressed = ~user_btn;
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// Button debounce
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reg btn_d1, btn_d2;
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reg [19:0] debounce_cnt;
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reg btn_stable, btn_stable_prev;
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wire btn_rise;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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btn_d1 <= 0; btn_d2 <= 0;
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debounce_cnt <= 0;
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btn_stable <= 0; btn_stable_prev <= 0;
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end else begin
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btn_d1 <= btn_pressed;
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btn_d2 <= btn_d1;
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if (btn_d2) begin
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if (debounce_cnt < 20'd500000)
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debounce_cnt <= debounce_cnt + 1;
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end else begin
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debounce_cnt <= 0;
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end
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btn_stable <= (debounce_cnt >= 20'd500000);
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btn_stable_prev <= btn_stable;
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end
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end
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assign btn_rise = btn_stable & ~btn_stable_prev;
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// Auto-start: trigger CPU 100ms after reset (no button needed)
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reg [31:0] auto_start_cnt;
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reg auto_start;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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auto_start_cnt <= 0;
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auto_start <= 0;
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end else if (!auto_start) begin
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if (auto_start_cnt >= 2700000) begin // 100ms at 27MHz
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auto_start <= 1;
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end else begin
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auto_start_cnt <= auto_start_cnt + 1;
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end
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end
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end
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// ── Blitter CPU Signals ────────────────────────────────────────
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wire cpu_busy;
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wire [5:0] cpu_led;
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wire cpu_uart_tx;
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wire [7:0] cpu_rdata;
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wire [11:0] cpu_mem_addr;
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wire [7:0] cpu_mem_wdata;
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wire cpu_mem_we;
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// ── Memory Map Signals ─────────────────────────────────────────
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wire [7:0] map_rdata;
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wire [31:0] map_q16_a;
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wire [31:0] map_q16_b;
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wire [2:0] map_q16_op;
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wire map_q16_trigger;
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wire [1:0] map_voltage_mode;
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wire [1:0] map_scale_select;
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wire [31:0] map_highs_pivot;
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wire map_highs_trigger;
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// ── Q16 LUT Core Signals ───────────────────────────────────────
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wire [31:0] q16_result;
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wire q16_valid;
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// ── Voltage Controller Signals ─────────────────────────────────
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wire [31:0] vctrl_dout;
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wire [1:0] vctrl_voltage;
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wire [4:0] vctrl_precision;
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wire vctrl_active;
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// ── Scale Space BRAM Signals ───────────────────────────────────
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wire [31:0] ss_dout;
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wire [31:0] ss_kernel_sum;
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// ── HiGHS Pivot Signals ────────────────────────────────────────
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wire [31:0] highs_result;
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wire highs_done;
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wire highs_write_en;
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wire [5:0] highs_write_idx;
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wire [31:0] highs_write_data;
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// ── Fractal Box Counter Signals ────────────────────────────────
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wire [31:0] frac_fd_q16;
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wire frac_fd_valid;
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wire [1:0] frac_voltage_mode;
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wire frac_mode_valid;
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// ── Spatial Hash BRAM Signals ─────────────────────────────────
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wire [15:0] sh_cell_density;
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wire [15:0] sh_neighbor_density;
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wire sh_query_done;
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// ── Spatial Hash Selector Signals ─────────────────────────────
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wire [1:0] sh_voltage_mode;
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wire sh_mode_valid;
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// ── Q16 LUT: use lower 16 bits of operands ────────────────────
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wire [15:0] q16_a_16 = map_q16_a[15:0];
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wire [15:0] q16_b_16 = map_q16_b[15:0];
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// ── Result mux: select result source based on address ──────────
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reg [31:0] result_latched;
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reg q16_done_reg;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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result_latched <= 0;
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q16_done_reg <= 0;
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end else begin
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if (map_q16_trigger && !q16_busy) begin
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q16_done_reg <= 0;
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end
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if (q16_valid && !q16_done_reg) begin
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result_latched <= q16_result;
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q16_done_reg <= 1;
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end
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end
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end
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reg q16_busy;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) q16_busy <= 0;
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else if (map_q16_trigger) q16_busy <= 1;
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else if (q16_valid) q16_busy <= 0;
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end
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// ── Instantiations ─────────────────────────────────────────────
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// Blitter6502OISC CPU
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Blitter6502OISC cpu (
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.clk(clk),
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.rst_n(rst_n),
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.start(auto_start),
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.busy(cpu_busy),
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.led(cpu_led),
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.uart_tx(cpu_uart_tx),
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.mem_we(1'b0),
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.mem_addr(16'd0),
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.mem_wdata(8'd0),
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.mem_rdata()
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);
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// Blitter Memory Map (8-bit CPU ↔ 32-bit peripherals)
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blitter_memory_map mem_map (
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.clk(clk),
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.rst_n(rst_n),
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.addr({4'b0, cpu_mem_addr}), // pad 12-bit to 16-bit
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.wdata(cpu_mem_wdata),
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.we(cpu_mem_we),
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.rdata(map_rdata),
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.q16_a(map_q16_a),
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.q16_b(map_q16_b),
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.q16_op(map_q16_op),
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.q16_trigger(map_q16_trigger),
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.voltage_mode(map_voltage_mode),
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.scale_select(map_scale_select),
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.highs_pivot_element(map_highs_pivot),
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.highs_trigger(map_highs_trigger)
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);
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// Q16 LUT Core (8 operations, 2-stage pipeline)
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q16_lut_core q16 (
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.clk(clk),
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.rst(rst),
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.op_select(map_q16_op),
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.a(q16_a_16),
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.b(q16_b_16),
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.result(q16_result),
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.valid(q16_valid)
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);
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// Voltage Mode Controller (4 BRAM modes)
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voltage_mode_controller vctrl (
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.clk(clk),
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.rst_n(rst_n),
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.mode(map_voltage_mode),
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.bram_addr(q16_a_16[9:0]),
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.bram_din(map_q16_b),
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.bram_we(map_q16_trigger),
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.morphic_amp(map_highs_pivot),
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.bram_dout(vctrl_dout),
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.voltage_level(vctrl_voltage),
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.precision_bits(vctrl_precision),
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.active(vctrl_active)
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);
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// Scale Space BRAM (4 Gaussian kernel banks)
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scale_space_bram ss_bram (
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.clk(clk),
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.we(1'b0),
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.bank_select(map_scale_select),
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.addr(q16_a_16[7:0]),
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.din(32'd0),
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.dout(ss_dout),
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.kernel_sum(ss_kernel_sum)
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);
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// FIX: Address-decoded trigger enables to prevent aliasing
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// Each module only fires when its specific address range is selected
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wire highs_addr_match = (cpu_mem_addr[11:8] == 4'h4); // $04xx range
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wire frac_addr_match = (cpu_mem_addr[11:8] == 4'h5); // $05xx range
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wire spatial_addr_match = (cpu_mem_addr[11:8] == 4'h6); // $06xx range
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wire highs_trigger_gated = map_highs_trigger & highs_addr_match;
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wire frac_trigger_gated = map_highs_trigger & frac_addr_match;
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wire spatial_trigger_gated = map_highs_trigger & spatial_addr_match;
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// HiGHS Pivot Accelerator
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highs_pivot_accelerator highs (
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.clk(clk),
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.rst_n(rst_n),
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.start(highs_trigger_gated),
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.pivot_element(map_highs_pivot),
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.column_in(map_q16_a),
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.column_idx(map_q16_b[5:0]),
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.result(highs_result),
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.done(highs_done),
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.write_en(highs_write_en),
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.write_idx(highs_write_idx),
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.write_data(highs_write_data)
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);
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// Fractal Box Counter (DBC algorithm, 8-bit input, Q16_16 FD output)
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fractal_box_counter #(
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.MAX_SCALE(8),
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.DATA_WIDTH(8)
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) frac_bc (
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.clk(clk),
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.rst_n(rst_n),
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.data_in(map_q16_a[7:0]),
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.data_valid(frac_trigger_gated),
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.data_count(map_q16_b[15:0]),
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.fd_q16(frac_fd_q16),
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.fd_valid(frac_fd_valid)
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);
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// Fractal FD → Voltage Mode Selector
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// Maps fractal dimension to voltage mode:
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// FD < 2.3 → STORE (0), FD < 2.6 → COMPUTE (1),
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// FD < 2.9 → APPROX (2), FD >= 2.9 → MORPHIC (3)
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fractal_fd_selector frac_sel (
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.clk(clk),
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.rst_n(rst_n),
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.fd_q16(frac_fd_q16),
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.fd_valid(frac_fd_valid),
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.voltage_mode(frac_voltage_mode),
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.mode_valid(frac_mode_valid)
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);
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// Spatial Hash BRAM (16×16×16 grid, 8 particles/cell, dual-port)
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// Insert: particle position from map_q16_a[3:0], trigger from map_highs_trigger
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// Query: query position from map_q16_b[3:0], trigger from map_q16_trigger
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spatial_hash_bram spatial_hash (
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.clk(clk),
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.rst_n(rst_n),
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.particle_x(map_q16_a[3:0]),
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.particle_y(map_q16_a[7:4]),
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.particle_z(map_q16_a[11:8]),
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.particle_valid(spatial_trigger_gated),
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.query_x(map_q16_b[3:0]),
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.query_y(map_q16_b[7:4]),
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.query_z(map_q16_b[11:8]),
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.query_valid(map_q16_trigger),
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.cell_density(sh_cell_density),
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.neighbor_density(sh_neighbor_density),
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.query_done(sh_query_done)
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);
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// Spatial Hash Density → Voltage Mode Selector
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// Maps particle density to voltage mode:
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// density < 10 → STORE, < 50 → COMPUTE, < 200 → APPROX, >= 200 → MORPHIC
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spatial_hash_selector sh_sel (
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.clk(clk),
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.rst_n(rst_n),
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.density_in(sh_cell_density),
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.density_valid(sh_query_done),
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.voltage_mode(sh_voltage_mode),
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.mode_valid(sh_mode_valid)
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);
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// ── LED Output ─────────────────────────────────────────────────
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// When CPU is busy: show running pattern (blinking)
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// When CPU is halted: show cpu_led (register values from Blitter)
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// Otherwise: show status
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reg [24:0] heartbeat;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) heartbeat <= 0;
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else heartbeat <= heartbeat + 1;
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end
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assign led = cpu_busy ? {1'b1, heartbeat[23], 1'b0, heartbeat[21], 1'b0, heartbeat[19]}
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: cpu_led; // Blitter's register output after halt
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// ── UART ───────────────────────────────────────────────────────
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assign uart_tx = cpu_uart_tx;
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endmodule
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