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57 lines
1.7 KiB
Verilog
57 lines
1.7 KiB
Verilog
`timescale 1ns / 1ps
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`include "voltage_mode_selector.v"
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// Fractal Dimension → Voltage Mode Selector
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// Maps computed fractal dimension (Q16_16) to a 2-bit voltage mode for the
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// voltage_mode_controller.
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//
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// FD < 2.3 → voltage_mode = 0 (STORE)
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// FD < 2.6 → voltage_mode = 1 (COMPUTE)
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// FD < 2.9 → voltage_mode = 2 (APPROX)
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// FD >= 2.9 → voltage_mode = 3 (MORPHIC)
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//
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// Thresholds in Q16_16:
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// 2.3 = 2 + 0.3 = 0x0002_4CCD (131072 + 19661 = 150733)
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// 2.6 = 2 + 0.6 = 0x0002_999A (131072 + 39322 = 170394)
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// 2.9 = 2 + 0.9 = 0x0002_E666 (131072 + 58982 = 190054)
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module fractal_fd_selector (
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input wire clk,
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input wire rst_n,
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input wire [31:0] fd_q16, // fractal dimension in Q16_16
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input wire fd_valid, // fd_q16 is valid
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output reg [1:0] voltage_mode, // 0=STORE, 1=COMPUTE, 2=APPROX, 3=MORPHIC
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output reg mode_valid // mode output is valid
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);
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localparam [31:0] THRESH_2_3 = 32'h0002_4CCD; // 2.3
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localparam [31:0] THRESH_2_6 = 32'h0002_999A; // 2.6
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localparam [31:0] THRESH_2_9 = 32'h0002_E666; // 2.9
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wire [1:0] sel_mode;
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voltage_mode_selector #(
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.THRESHOLD1(THRESH_2_3),
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.THRESHOLD2(THRESH_2_6),
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.THRESHOLD3(THRESH_2_9)
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) sel_inst (
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.clk(clk),
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.value(fd_q16),
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.mode(sel_mode)
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);
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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voltage_mode <= 2'b00;
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mode_valid <= 1'b0;
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end else begin
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mode_valid <= 1'b0;
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if (fd_valid) begin
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voltage_mode <= sel_mode;
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mode_valid <= 1'b1;
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end
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end
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end
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endmodule
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