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HiGHS Optimization: - qubo_highs.py: QUBO→MIP reformulation via highspy (exact, not approximate) - solve_route_lp: TSP/VRP assignment relaxation for RouteCost 39-node graph - scale_space_solver.py: multi-scale optimization (coarse LP → fine MIP) - Gaussian kernels in Q16_16, voltage↔scale mapping - alphaproof_loop.py: Ollama → lake build → feedback proof search Lean Formalization: - AdjugateMatrix.lean: division-free matrix inversion (291 lines, 3300 jobs, 0 errors) - det2/det4/det8 via cofactor expansion, all Q16_16 - adjugate, matrixInverse, cayleyTransform - 7 #eval witnesses all pass FPGA (Tang Nano 9K): - voltage_mode_controller.v: 4-mode BRAM (STORE/COMPUTE/APPROX/MORPHIC) - scale_space_bram.v: 4 Gaussian kernel banks (σ=0.25/0.50/0.75/1.00) - highs_pivot_accelerator.v: 3-stage pipeline, Q16_16 division, 64-element columns - blitter_memory_map.v: 8-bit CPU ↔ 32-bit Q16 bridge, full I/O map at $8000
108 lines
3.5 KiB
Verilog
108 lines
3.5 KiB
Verilog
`timescale 1ns / 1ps
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// HiGHS Pivot Accelerator for Tang Nano 9K (GW1NR-9C)
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// Simplex pivot: column[j] = column[j] / pivot_element
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// 3-stage pipeline: load / divide / writeback
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// Q16_16 division inline: result = (column_val << 16) / pivot_element
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// 64-element column support
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module highs_pivot_accelerator (
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input wire clk,
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input wire rst_n,
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input wire start,
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input wire [31:0] pivot_element,
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input wire [31:0] column_in,
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input wire [5:0] column_idx,
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output reg [31:0] result,
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output reg done,
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output reg write_en,
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output reg [5:0] write_idx,
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output reg [31:0] write_data
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);
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// State machine
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localparam IDLE = 2'b00;
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localparam LOAD = 2'b01;
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localparam DIVIDE = 2'b10;
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localparam WRITEBACK = 2'b11;
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reg [1:0] state;
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reg [5:0] elem_count; // tracks which element we're processing (0..63)
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reg [5:0] elem_count_d1; // delayed count for pipeline
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// Pipeline registers
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reg [31:0] column_val_reg; // stage 1 output
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reg [63:0] dividend; // stage 2: column_val << 16 for Q16_16 division
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reg [31:0] pivot_reg; // latched pivot element
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// Division result
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reg [31:0] div_result;
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always @(posedge clk) begin
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if (!rst_n) begin
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state <= IDLE;
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result <= 32'd0;
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done <= 1'b0;
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write_en <= 1'b0;
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write_idx <= 6'd0;
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write_data <= 32'd0;
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elem_count <= 6'd0;
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elem_count_d1 <= 6'd0;
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column_val_reg <= 32'd0;
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dividend <= 64'd0;
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pivot_reg <= 32'd0;
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div_result <= 32'd0;
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end else begin
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// Default: deassert single-cycle pulses
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write_en <= 1'b0;
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done <= 1'b0;
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case (state)
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IDLE: begin
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if (start) begin
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pivot_reg <= pivot_element;
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elem_count <= 6'd0;
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state <= LOAD;
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end
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end
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LOAD: begin
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// Stage 1: Latch column input
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column_val_reg <= column_in;
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elem_count_d1 <= elem_count;
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dividend <= {32'd0, column_in} << 16; // Q16_16 shift
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state <= DIVIDE;
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end
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DIVIDE: begin
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// Stage 2: Perform division
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// result = (column_val << 16) / pivot_element
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if (pivot_reg != 32'd0) begin
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div_result <= dividend[63:0] / {32'd0, pivot_reg};
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end else begin
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div_result <= 32'h7FFFFFFF; // saturate on divide-by-zero
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end
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state <= WRITEBACK;
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end
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WRITEBACK: begin
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// Stage 3: Write result back
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write_en <= 1'b1;
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write_idx <= elem_count_d1;
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write_data <= div_result;
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result <= div_result;
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if (elem_count_d1 == 6'd63) begin
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// All 64 elements processed
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done <= 1'b1;
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state <= IDLE;
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end else begin
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elem_count <= elem_count_d1 + 6'd1;
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state <= LOAD;
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end
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end
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endcase
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end
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end
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endmodule
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