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ba203ca971
Ported from ScaleSpaceSynth (WebGPU particle simulator): - 64×64×64 spatial hash, 32 particles/cell, lock-free insertion - Curl noise: divergence-free 3D turbulence - Pairwise forces: attractive (ratio>0.15) + repulsive (ratio<=0.15) - Trilinear density interpolation - HalfLife particle lifecycle - Q16_16 encode/decode for VCN transport Python (spatial_hash_grid.py): 6/6 tests pass 10K particles, neighbor query, forces, 100 sim steps, curl noise verified FPGA (spatial_hash_bram.v): 16×16×16 grid, dual-port BRAM, 27-cycle neighbor scan Density → voltage mode selector (STORE/COMPUTE/APPROX/MORPHIC) Integrated into research_stack_top.v Same pattern as ScaleSpaceSynth GPU: GPU: atomicAdd for lock-free cell assignment FPGA: BRAM read-modify-write for cell assignment Ray: content-addressed ObjectRef for lock-free reads All: partition space → compute density → find structure at multiple scales
72 lines
2.9 KiB
Verilog
72 lines
2.9 KiB
Verilog
`timescale 1ns / 1ps
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// Spatial Hash Density → Voltage Mode Selector
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// Maps particle density from spatial_hash_bram to voltage mode.
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//
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// Thresholds (8-bit density, max 255):
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// density < 10 → STORE (2'b00) — sparse, low activity
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// density < 50 → COMPUTE (2'b01) — moderate, full precision
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// density < 200 → APPROX (2'b10) — dense, reduced precision
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// density >= 200 → MORPHIC (2'b11) — maximum density, morphic mode
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//
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// Q16_16 arithmetic for all internal computations.
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module spatial_hash_selector (
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input wire clk,
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input wire rst_n,
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input wire [15:0] density_in, // particle density (from spatial_hash_bram)
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input wire density_valid, // density valid strobe
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output reg [1:0] voltage_mode, // selected voltage mode
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output reg mode_valid // mode output valid pulse
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);
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// ── Density Thresholds ────────────────────────────────────────
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// Stored as 16-bit values (upper 8 bits are integer part)
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localparam [15:0] THRESH_SPARSE = 16'd10; // < 10 → STORE
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localparam [15:0] THRESH_MODERATE = 16'd50; // < 50 → COMPUTE
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localparam [15:0] THRESH_DENSE = 16'd200; // < 200 → APPROX
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// >= 200 → MORPHIC
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// ── Voltage Mode Encoding ─────────────────────────────────────
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localparam MODE_STORE = 2'b00;
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localparam MODE_COMPUTE = 2'b01;
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localparam MODE_APPROX = 2'b10;
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localparam MODE_MORPHIC = 2'b11;
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// ── Pipeline Stage 1: latch input ─────────────────────────────
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reg [15:0] density_pipe;
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reg valid_pipe;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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density_pipe <= 16'd0;
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valid_pipe <= 1'b0;
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end else begin
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density_pipe <= density_in;
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valid_pipe <= density_valid;
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end
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end
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// ── Pipeline Stage 2: threshold comparison & output ───────────
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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voltage_mode <= MODE_STORE;
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mode_valid <= 1'b0;
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end else begin
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mode_valid <= valid_pipe;
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if (!valid_pipe) begin
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// Hold previous mode when no new data
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end else if (density_pipe < THRESH_SPARSE) begin
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voltage_mode <= MODE_STORE;
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end else if (density_pipe < THRESH_MODERATE) begin
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voltage_mode <= MODE_COMPUTE;
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end else if (density_pipe < THRESH_DENSE) begin
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voltage_mode <= MODE_APPROX;
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end else begin
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voltage_mode <= MODE_MORPHIC;
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end
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end
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end
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endmodule
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