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314 lines
10 KiB
Verilog
314 lines
10 KiB
Verilog
// Tang Nano 9K Hutter/metaprobe symbol surface.
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//
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// UART frame in:
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// A5 01 seq opcode len payload[len] crc8
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//
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// Current opcode:
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// 0x10 = substitute metaprobe/Hutter text token bytes through a tiny LUT.
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//
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// UART frame out:
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// A6 01 seq status 06 opcode hash_hi hash_lo mapped literal crc8
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//
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// LED reservoir address surface:
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// logical LED address = {PBACS/CMYK route state, mapped_count[3:0]}
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// physical LEDs are active low, so pins drive ~logical_address.
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// This gives the loaded FPGA a tiny visible reservoir/state address bus:
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// bits [5:4] = PBACS/CMYK route state
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// bits [3:0] = mapped-symbol bucket
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//
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// The response is a receipt, not a compressed artifact. The host keeps the full
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// codec and verifies this hardware witness against software substitution.
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`timescale 1ns / 1ps
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module tangnano9k_hutter_symbol_surface (
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input clk, // 27 MHz
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input rst_n, // Reset button, active low
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input uart_rx_pin,
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output uart_tx_pin,
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output [5:0] led // active low
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);
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localparam MAGIC_IN = 8'hA5;
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localparam MAGIC_OUT = 8'hA6;
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localparam VERSION = 8'h01;
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localparam OP_SUBST = 8'h10;
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localparam RX_WAIT_MAGIC = 4'd0;
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localparam RX_VERSION = 4'd1;
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localparam RX_SEQ = 4'd2;
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localparam RX_OPCODE = 4'd3;
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localparam RX_LEN = 4'd4;
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localparam RX_PAYLOAD = 4'd5;
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localparam RX_CRC = 4'd6;
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localparam RX_PROCESS = 4'd7;
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localparam TX_LOAD = 4'd8;
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localparam TX_WAIT = 4'd9;
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wire [7:0] rx_data;
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wire rx_done;
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reg [7:0] tx_data;
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reg tx_start;
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wire tx_busy;
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reg [3:0] state;
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reg [7:0] seq;
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reg [7:0] opcode;
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reg [4:0] payload_len;
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reg [4:0] payload_index;
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reg [7:0] payload [0:15];
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reg [7:0] frame_crc;
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reg [7:0] calc_crc;
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reg [15:0] rolling_hash;
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reg [7:0] mapped_count;
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reg [7:0] literal_count;
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reg [7:0] status;
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reg [3:0] tx_index;
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reg [7:0] tx_crc;
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reg [7:0] last_token;
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reg [18:0] rx_idle_cycles;
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localparam RX_TIMEOUT_CYCLES = 19'd270000; // ~10 ms at 27 MHz
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wire [3:0] subst_code;
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wire subst_hit;
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wire pbacs_valid;
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wire [15:0] pbacs_value_q16;
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wire [1:0] pbacs_cmyk_state;
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wire pbacs_bit_out;
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wire signed [17:0] pbacs_error_acc;
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wire [15:0] pbacs_stress_acc;
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assign pbacs_valid = (state == RX_PROCESS) && (payload_index < payload_len);
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assign pbacs_value_q16 = {subst_hit, subst_code, 11'd0};
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hutter_symbol_substitution_core subst (
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.symbol(payload[payload_index]),
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.code(subst_code),
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.hit(subst_hit)
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);
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pbacs_1bit_transport_core pbacs (
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.clk(clk),
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.rst_n(rst_n),
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.clear(state == RX_CRC && rx_done),
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.valid(pbacs_valid),
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.value_q16(pbacs_value_q16),
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.threshold_q16(16'h8000),
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.mismatch_q8({literal_count[3:0], mapped_count[3:0]}),
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.mask_popcount({3'd0, subst_hit}),
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.bit_out(pbacs_bit_out),
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.error_acc(pbacs_error_acc),
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.stress_acc(pbacs_stress_acc),
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.cmyk_state(pbacs_cmyk_state)
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);
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uart_rx rx_inst (
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.clk(clk),
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.rst_n(rst_n),
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.rx_pin(uart_rx_pin),
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.rx_data(rx_data),
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.rx_done(rx_done)
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);
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uart_tx tx_inst (
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.clk(clk),
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.rst_n(rst_n),
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.tx_start(tx_start),
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.tx_data(tx_data),
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.uart_tx(uart_tx_pin),
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.tx_busy(tx_busy)
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);
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function [7:0] crc8_next;
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input [7:0] crc;
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input [7:0] data;
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begin
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// Cheap XOR checksum for Surface-0. Replace with polynomial CRC
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// when the frame contract stabilizes.
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crc8_next = crc ^ data;
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end
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endfunction
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function [7:0] tx_byte_at;
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input [3:0] idx;
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begin
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case (idx)
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4'd0: tx_byte_at = MAGIC_OUT;
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4'd1: tx_byte_at = VERSION;
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4'd2: tx_byte_at = seq;
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4'd3: tx_byte_at = status;
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4'd4: tx_byte_at = 8'd6;
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4'd5: tx_byte_at = opcode;
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4'd6: tx_byte_at = rolling_hash[15:8];
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4'd7: tx_byte_at = rolling_hash[7:0];
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4'd8: tx_byte_at = mapped_count;
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4'd9: tx_byte_at = literal_count;
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4'd10: tx_byte_at = tx_crc;
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default: tx_byte_at = 8'h00;
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endcase
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end
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endfunction
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integer i;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= RX_WAIT_MAGIC;
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seq <= 8'h00;
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opcode <= 8'h00;
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payload_len <= 5'd0;
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payload_index <= 5'd0;
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frame_crc <= 8'h00;
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calc_crc <= 8'h00;
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rolling_hash <= 16'hACE1;
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mapped_count <= 8'd0;
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literal_count <= 8'd0;
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status <= 8'h00;
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tx_index <= 4'd0;
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tx_crc <= 8'h00;
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tx_data <= 8'h00;
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tx_start <= 1'b0;
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last_token <= 8'h00;
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rx_idle_cycles <= 19'd0;
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for (i = 0; i < 16; i = i + 1) begin
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payload[i] <= 8'h00;
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end
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end else begin
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tx_start <= 1'b0;
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if (rx_done || state == RX_WAIT_MAGIC || state == RX_PROCESS ||
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state == TX_LOAD || state == TX_WAIT) begin
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rx_idle_cycles <= 19'd0;
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end else if (rx_idle_cycles >= RX_TIMEOUT_CYCLES) begin
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state <= RX_WAIT_MAGIC;
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calc_crc <= 8'h00;
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payload_index <= 5'd0;
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rx_idle_cycles <= 19'd0;
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end else begin
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rx_idle_cycles <= rx_idle_cycles + 19'd1;
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end
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// A fresh magic byte can resynchronize the framed stream from any
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// receive state. Surface-0 payloads do not use 0xA5.
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if (rx_done && rx_data == MAGIC_IN && state != TX_LOAD && state != TX_WAIT) begin
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calc_crc <= rx_data;
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payload_index <= 5'd0;
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state <= RX_VERSION;
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end else case (state)
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RX_WAIT_MAGIC: begin
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if (rx_done && rx_data == MAGIC_IN) begin
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calc_crc <= rx_data;
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state <= RX_VERSION;
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end
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end
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RX_VERSION: begin
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if (rx_done) begin
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calc_crc <= crc8_next(calc_crc, rx_data);
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state <= (rx_data == VERSION) ? RX_SEQ : RX_WAIT_MAGIC;
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end
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end
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RX_SEQ: begin
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if (rx_done) begin
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seq <= rx_data;
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calc_crc <= crc8_next(calc_crc, rx_data);
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state <= RX_OPCODE;
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end
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end
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RX_OPCODE: begin
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if (rx_done) begin
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opcode <= rx_data;
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calc_crc <= crc8_next(calc_crc, rx_data);
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state <= RX_LEN;
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end
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end
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RX_LEN: begin
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if (rx_done) begin
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payload_len <= (rx_data[4:0] > 5'd16) ? 5'd16 : rx_data[4:0];
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payload_index <= 5'd0;
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calc_crc <= crc8_next(calc_crc, rx_data);
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state <= (rx_data == 8'd0) ? RX_CRC : RX_PAYLOAD;
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end
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end
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RX_PAYLOAD: begin
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if (rx_done) begin
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payload[payload_index] <= rx_data;
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last_token <= rx_data;
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calc_crc <= crc8_next(calc_crc, rx_data);
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if (payload_index + 5'd1 >= payload_len) begin
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state <= RX_CRC;
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end
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payload_index <= payload_index + 5'd1;
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end
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end
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RX_CRC: begin
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if (rx_done) begin
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frame_crc <= rx_data;
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payload_index <= 5'd0;
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rolling_hash <= 16'hACE1;
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mapped_count <= 8'd0;
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literal_count <= 8'd0;
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if (rx_data != calc_crc) begin
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status <= 8'hE1;
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state <= TX_LOAD;
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end else if (opcode != OP_SUBST) begin
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status <= 8'hE2;
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state <= TX_LOAD;
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end else begin
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status <= 8'h00;
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state <= RX_PROCESS;
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end
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end
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end
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RX_PROCESS: begin
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if (payload_index < payload_len) begin
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rolling_hash <= {rolling_hash[14:0], rolling_hash[15]} ^
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{11'd0, subst_hit, subst_code};
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if (subst_hit) begin
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mapped_count <= mapped_count + 8'd1;
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end else begin
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literal_count <= literal_count + 8'd1;
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end
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payload_index <= payload_index + 5'd1;
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end else begin
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state <= TX_LOAD;
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end
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end
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TX_LOAD: begin
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tx_index <= 4'd0;
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tx_crc <= MAGIC_OUT ^ VERSION ^ seq ^ status ^ 8'd6 ^ opcode ^
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rolling_hash[15:8] ^ rolling_hash[7:0] ^
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mapped_count ^ literal_count;
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state <= TX_WAIT;
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end
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TX_WAIT: begin
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if (!tx_busy && !tx_start) begin
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tx_data <= tx_byte_at(tx_index);
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tx_start <= 1'b1;
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if (tx_index == 4'd10) begin
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state <= RX_WAIT_MAGIC;
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end else begin
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tx_index <= tx_index + 4'd1;
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end
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end
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end
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default: state <= RX_WAIT_MAGIC;
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endcase
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end
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end
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wire [5:0] led_reservoir_address;
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assign led_reservoir_address = {pbacs_cmyk_state, mapped_count[3:0]};
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assign led = ~led_reservoir_address;
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endmodule
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