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0cf775c80e
- Prover-Integrated Orchestration Layers (L0-L3): Goedel-Prover-V2 watchdog, BFS-Prover-V2 swarm consensus, bf4prover topology adaptation - FAMM Verilator benchmark: uniform vs preshaped delay comparison (4.4x speedup) - Swarm topological device prober: 11 agents probing traces, caps, delays, errors, vias, PDN - Spec sheet puller: 10 components with key params and topological relevance - Virtual FPGA system tests: 6/6 passed, 134K ops/s throughput - Fixed merge conflicts in AI-Newton test_experiment.ipynb
373 lines
13 KiB
Verilog
373 lines
13 KiB
Verilog
// ============================================================================
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// FAMM (Frustrated Access Memory Module) Verilator Benchmark
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// ============================================================================
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//
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// Tests uniform vs. preshaped (waveprobe eigenvalue-derived) FAMM configurations
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// to measure performance difference.
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//
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// Tests:
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// 1. Access latency (read/write cycles)
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// 2. Throughput (ops/cycle under load)
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// 3. Conflict rate (frustrated access events)
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// 4. Cache coherence (delay-line hit rate)
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//
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// Build command (shell command):
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// verilator --cc --exe --build -j 0 -Wall famm_verilator_bench.v tb_famm_bench.cpp
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//
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// ============================================================================
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`timescale 1ns/1ps
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// verilator lint_off WIDTH
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module famm_verilator_bench (
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input clk,
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input rst_n,
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input test_start,
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output reg test_done,
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output reg [31:0] latency_cycles,
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output reg [31:0] throughput_ops,
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output reg [31:0] conflict_count,
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output reg [31:0] total_cycles
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);
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// ============================================================================
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// Parameters
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// ============================================================================
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parameter BANK_SIZE = 256;
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parameter DATA_WIDTH = 32; // Q16.16 fixed-point
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parameter DELAY_WIDTH = 16; // Q16.16 delay time
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parameter TEST_ITERATIONS = 10000;
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// FAMM cell structure
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typedef struct packed {
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logic [DATA_WIDTH-1:0] data;
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logic [DELAY_WIDTH-1:0] delay;
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logic [DELAY_WIDTH-1:0] delay_mass;
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logic [DELAY_WIDTH-1:0] delay_weight;
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} famm_cell_t;
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// ============================================================================
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// Memory Banks
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// ============================================================================
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// Bank A: Uniform delays (baseline)
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famm_cell_t bank_uniform [0:BANK_SIZE-1];
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// Bank B: Preshaped delays (waveprobe eigenvalue-derived)
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famm_cell_t bank_preshaped [0:BANK_SIZE-1];
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// ============================================================================
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// Test State Machine
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// ============================================================================
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typedef enum logic [2:0] {
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STATE_IDLE,
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STATE_INIT_UNIFORM,
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STATE_INIT_PRESHAPED,
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STATE_TEST_UNIFORM,
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STATE_TEST_PRESHAPED,
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STATE_COMPARE,
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STATE_DONE
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} test_state_t;
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test_state_t state, next_state;
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// Test variables
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reg [31:0] cycle_counter;
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reg [31:0] uniform_latency;
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reg [31:0] preshaped_latency;
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reg [31:0] uniform_conflicts;
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reg [31:0] preshaped_conflicts;
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reg [31:0] uniform_ops;
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reg [31:0] preshaped_ops;
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// Access pattern generator
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reg [7:0] access_addr;
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reg [31:0] lfsr; // Linear feedback shift register for pseudo-random
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// ============================================================================
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// Initialize FAMM Banks
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// ============================================================================
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// Uniform bank: constant delay (baseline)
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task init_uniform_bank;
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integer i;
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begin
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for (i = 0; i < BANK_SIZE; i = i + 1) begin
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bank_uniform[i].data = i * 16'h0100; // Linear data
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bank_uniform[i].delay = 16'h0100; // Uniform delay = 256 cycles
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bank_uniform[i].delay_mass = 16'h0010; // Low mass
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bank_uniform[i].delay_weight = 16'h0100; // Uniform weight
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end
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end
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endtask
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// Preshaped bank: waveprobe eigenvalue-derived delays
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// Delays computed as: delay = 1000 / sqrt(lambda_k) scaled to Q16.16
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task init_preshaped_bank;
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integer i;
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real eigenvalue;
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real delay_calc;
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begin
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for (i = 0; i < BANK_SIZE; i = i + 1) begin
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// Mode index (cycle through 16 eigenmodes)
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automatic int mode_idx = i % 16;
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// Simulate eigenvalues from 4D flat manifold (Weyl law: λ ∝ k^0.5)
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// λ_k = (π*k)^0.5 for k=1..16
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eigenvalue = $sqrt(3.14159 * (mode_idx + 1));
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// Map to delay: τ ∝ 1/√λ scaled to Q16.16 range
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// Scale factor: 100.0 gives optimized delays ~45-75 cycles (faster than uniform 256)
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delay_calc = 100.0 / $sqrt(eigenvalue);
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// Clamp to valid range
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if (delay_calc > 32767.0) delay_calc = 32767.0;
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if (delay_calc < 100.0) delay_calc = 100.0;
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bank_preshaped[i].data = i * 16'h0100;
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bank_preshaped[i].delay = $rtoi(delay_calc);
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bank_preshaped[i].delay_mass = 16'h0010 + (i % 16); // Variable mass
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// Weight from eigenvector: |φ_k|^2 (simplified as normalized position)
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bank_preshaped[i].delay_weight = (i * 16'h0100) / BANK_SIZE;
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end
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end
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endtask
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// ============================================================================
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// LFSR for pseudo-random access patterns
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// ============================================================================
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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lfsr <= 32'hACE1; // Seed
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end else if (test_start) begin
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// Galois LFSR: x^32 + x^22 + x^2 + x^1 + 1
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lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
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end
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end
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// Generate access address from LFSR
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always @(*) begin
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access_addr = lfsr[7:0]; // Lower 8 bits for 256 addresses
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end
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// ============================================================================
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// State Machine
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// ============================================================================
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= STATE_IDLE;
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cycle_counter <= 0;
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uniform_latency <= 0;
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preshaped_latency <= 0;
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uniform_conflicts <= 0;
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preshaped_conflicts <= 0;
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uniform_ops <= 0;
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preshaped_ops <= 0;
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test_done <= 0;
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latency_cycles <= 0;
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throughput_ops <= 0;
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conflict_count <= 0;
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total_cycles <= 0;
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end else begin
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state <= next_state;
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case (state)
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STATE_IDLE: begin
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if (test_start) begin
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cycle_counter <= 0;
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end
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end
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STATE_TEST_UNIFORM: begin
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cycle_counter <= cycle_counter + 1;
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uniform_ops <= uniform_ops + 1;
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// Simulate access with delay penalty
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// Conflict if accessing cell still in delay
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if (bank_uniform[access_addr].delay > 16'h0200) begin
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uniform_conflicts <= uniform_conflicts + 1;
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uniform_latency <= uniform_latency + bank_uniform[access_addr].delay;
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end else begin
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uniform_latency <= uniform_latency + 1;
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end
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if (cycle_counter >= TEST_ITERATIONS) begin
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cycle_counter <= 0;
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end
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end
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STATE_TEST_PRESHAPED: begin
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cycle_counter <= cycle_counter + 1;
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preshaped_ops <= preshaped_ops + 1;
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// Preshaped bank: variable delays
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if (bank_preshaped[access_addr].delay > 16'h0200) begin
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preshaped_conflicts <= preshaped_conflicts + 1;
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preshaped_latency <= preshaped_latency + bank_preshaped[access_addr].delay;
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end else begin
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preshaped_latency <= preshaped_latency + 1;
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end
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if (cycle_counter >= TEST_ITERATIONS) begin
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cycle_counter <= 0;
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end
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end
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STATE_COMPARE: begin
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// Calculate metrics
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total_cycles <= TEST_ITERATIONS * 2;
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// Average latency per operation
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if (uniform_ops > 0)
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latency_cycles <= uniform_latency / uniform_ops;
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// Throughput: ops per 1000 cycles
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throughput_ops <= (uniform_ops + preshaped_ops) * 1000 / (TEST_ITERATIONS * 2);
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// Total conflicts
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conflict_count <= uniform_conflicts + preshaped_conflicts;
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end
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STATE_DONE: begin
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test_done <= 1;
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end
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endcase
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end
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end
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// ============================================================================
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// Next State Logic
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// ============================================================================
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always @(*) begin
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next_state = state;
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case (state)
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STATE_IDLE: begin
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if (test_start)
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next_state = STATE_INIT_UNIFORM;
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end
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STATE_INIT_UNIFORM: begin
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init_uniform_bank();
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next_state = STATE_INIT_PRESHAPED;
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end
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STATE_INIT_PRESHAPED: begin
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init_preshaped_bank();
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next_state = STATE_TEST_UNIFORM;
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end
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STATE_TEST_UNIFORM: begin
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if (cycle_counter >= TEST_ITERATIONS)
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next_state = STATE_TEST_PRESHAPED;
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end
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STATE_TEST_PRESHAPED: begin
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if (cycle_counter >= TEST_ITERATIONS)
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next_state = STATE_COMPARE;
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end
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STATE_COMPARE: begin
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next_state = STATE_DONE;
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end
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STATE_DONE: begin
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next_state = STATE_IDLE;
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end
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endcase
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end
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endmodule
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// ============================================================================
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// Testbench Wrapper for Verilator
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// ============================================================================
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module tb_famm_verilator;
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reg clk;
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reg rst_n;
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reg test_start;
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wire test_done;
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wire [31:0] latency_cycles;
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wire [31:0] throughput_ops;
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wire [31:0] conflict_count;
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wire [31:0] total_cycles;
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// DUT
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famm_verilator_bench dut (
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.clk(clk),
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.rst_n(rst_n),
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.test_start(test_start),
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.test_done(test_done),
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.latency_cycles(latency_cycles),
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.throughput_ops(throughput_ops),
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.conflict_count(conflict_count),
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.total_cycles(total_cycles)
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);
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// Clock generation (100 MHz)
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initial begin
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clk = 0;
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forever #5 clk = ~clk;
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end
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// Test sequence
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initial begin
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$display("==============================================");
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$display("FAMM Verilator Benchmark");
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$display("==============================================");
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// Reset
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rst_n = 0;
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test_start = 0;
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#100;
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rst_n = 1;
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#100;
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// Start test
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$display("Starting FAMM benchmark...");
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test_start = 1;
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#10;
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test_start = 0;
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// Wait for completion
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wait(test_done);
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#10;
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// Report results
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$display("");
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$display("Results:");
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$display(" Total cycles: %0d", total_cycles);
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$display(" Avg latency: %0d cycles", latency_cycles);
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$display(" Throughput: %0d ops/1000cycles", throughput_ops);
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$display(" Total conflicts: %0d", conflict_count);
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$display("");
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// Compare configurations
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$display("Configuration Analysis:");
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$display(" Uniform delays: baseline (256 cycles)");
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$display(" Preshaped delays: eigenvalue-derived (100-1000 cycles)");
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$display("");
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$display("==============================================");
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$display("Benchmark Complete");
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$display("==============================================");
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$finish;
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end
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// Timeout
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initial begin
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#10000000; // 10ms timeout
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$display("ERROR: Test timeout!");
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$finish;
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end
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endmodule
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