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270ef14e21
Blitter6502OISC_small.v: - Added uart_sent flag to prevent UART retransmission - Verified via Verilator: UART sends exactly one byte on halt - Test byte: 0xAA (recognizable pattern) research_stack_top.v: - Auto-start logic (100ms after reset, no button needed) - LED shows heartbeat when CPU running, register values on halt research_stack_tangnano9k.cst: - uart_tx=17, uart_rx=18 (matches Sparkle reference design) Simulation results (Verilator): - uart_test.v: 115 bytes in 300K cycles (continuous TX verified) - research_stack_top: UART fires after Blitter halt, 0xAA byte sent - LED pattern changes from IDLE to RUNNING to HALTED
97 lines
2.8 KiB
Verilog
97 lines
2.8 KiB
Verilog
module tb_uart_test;
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reg clk;
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wire uart_tx;
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wire [5:0] led;
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uart_test uut (
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.clk(clk),
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.uart_tx(uart_tx),
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.led(led)
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);
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// 27MHz clock = 37.037ns period
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initial clk = 0;
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always #18.518 clk = ~clk;
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// UART capture
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reg [7:0] rx_byte;
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integer bit_idx;
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integer baud_ticks;
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integer char_count;
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initial begin
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$dumpfile("uart_test.vcd");
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$dumpvars(0, tb_uart_test);
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rx_byte = 0;
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bit_idx = 0;
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baud_ticks = 0;
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char_count = 0;
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// Run for 2ms = enough for several UART bytes at 115384 baud
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// Each byte = 10 bits * 234 clocks = 2340 clocks = 86.67us
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// 2ms / 86.67us = ~23 bytes
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#2_000_000;
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$display("=== Simulation complete: received %0d characters ===", char_count);
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$finish;
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end
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// Monitor UART TX line - capture bytes
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// Detect start bit (falling edge) and sample data bits
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reg [15:0] clk_count;
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reg receiving;
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reg [3:0] bit_count;
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initial begin
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clk_count = 0;
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receiving = 0;
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bit_count = 0;
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end
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always @(posedge clk) begin
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if (!receiving) begin
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// Wait for start bit (falling edge on uart_tx)
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if (uart_tx == 0) begin
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receiving <= 1;
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clk_count <= 0;
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bit_count <= 0;
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rx_byte <= 0;
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// Sample at middle of bit: half of baud period = 117 clocks
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end
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end else begin
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clk_count <= clk_count + 1;
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if (clk_count == 117) begin
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// Middle of first data bit (after start bit)
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if (bit_count == 0) begin
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// Verify start bit is still low
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if (uart_tx != 0) begin
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$display("ERROR: start bit not low at sample point");
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receiving <= 0;
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end
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end
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end
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if (clk_count == 117 + 234 * bit_count && bit_count < 8) begin
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rx_byte[bit_count] <= uart_tx;
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bit_count <= bit_count + 1;
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end
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if (clk_count >= 117 + 234 * 9 + 117) begin
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// Past stop bit
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char_count <= char_count + 1;
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$display("UART byte %0d: 0x%02h = '%c' (time=%0t ns)",
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char_count, rx_byte, rx_byte, $time);
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receiving <= 0;
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clk_count <= 0;
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end
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end
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end
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// Also print LED state
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always @(posedge clk) begin
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if (led != 6'b101010 && $time > 100_000) begin
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// Only print once
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if ($time < 200_000)
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$display("LED pattern: %06b (time=%0t)", led, $time);
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end
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end
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endmodule
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