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77 lines
2.5 KiB
Verilog
77 lines
2.5 KiB
Verilog
/*
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* PBACS REV3 — Policy-Based Adaptive Constraint System
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* Low-Level Signal Transport Layer (Formal Extractions)
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*
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* Target: Tang Nano 9K (Gowin GW1NR-9)
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* Specification: linear/RES-2311
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*
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* Formal Anchor: Semantics.PBACSSignal
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*/
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module pbacs_rev3 (
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input wire clk,
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input wire reset_n,
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input wire signed [15:0] sample_in,
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output reg b_t,
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output reg [1:0] policy_state,
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output reg [31:0] pressure_out
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);
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// L2 Phi-accumulator (Golden Ratio constant: 106070)
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reg [31:0] phi;
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// L1 Error accumulator
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reg signed [31:0] error;
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// L4 Pressure accumulator (SLUQ)
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reg [31:0] pressure;
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// Threshold constant from specification
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localparam signed [31:0] THRESH_POS = 32768;
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localparam signed [31:0] THRESH_NEG = -32768;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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phi <= 0;
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error <= 0;
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pressure <= 0;
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b_t <= 0;
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policy_state <= 2'b00; // CYAN
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end else begin
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// Step 1: Phi increment
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phi <= phi + 32'd106070;
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// Step 2: Threshold lookup (MSB-based simplification)
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// L2: theta_t = LUT[phi]
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wire signed [31:0] theta_t = (phi[31]) ? THRESH_POS : THRESH_NEG;
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// Step 3 & 4: Error Accumulation and Symbol Decision
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// b_t = (v_t + e_t-1) > theta_t
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if ((sample_in + error) > theta_t) begin
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b_t <= 1'b1;
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error <= sample_in + error - theta_t;
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end else begin
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b_t <= 1'b0;
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error <= sample_in + error;
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end
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// Step 5-8: Pressure Management (SLUQ)
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// stress = |e_next|
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wire [31:0] stress = (error[31]) ? -error : error;
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// exponential pressure tracking (0.9 decay + 0.1 gain)
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// pressure <= (pressure * 0.9) + (stress * 0.1)
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// Using 10-bit shifts for approximation: (P*921 + S*103) >> 10
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pressure <= (pressure * 32'd921 + stress * 32'd103) >> 10;
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// Policy Transition (CMYK)
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if (pressure > 32'd50000) policy_state <= 2'b11; // BLACK (Halt)
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else if (pressure > 32'd30000) policy_state <= 2'b10; // YELLOW (Warning)
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else if (pressure > 32'd10000) policy_state <= 2'b01; // MAGENTA (Active)
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else policy_state <= 2'b00; // CYAN (Idle)
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pressure_out <= pressure;
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end
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end
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endmodule
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