mirror of
https://github.com/allaunthefox/Research-Stack.git
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242 lines
10 KiB
Python
242 lines
10 KiB
Python
#!/usr/bin/env python3
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"""
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USB Controller Computational Repurposing
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Analyzes USB controllers for general-purpose computation capabilities.
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"""
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import json
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from pathlib import Path
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from typing import Dict, List, Optional
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# Paths
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OUTPUT_DIR = Path("/home/allaun/Documents/Research Stack/out")
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class USBComputationalController:
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"""Analyzes USB controllers for general computation."""
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def __init__(self):
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self.usb_controllers = {
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"10:00.0": {
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"name": "AMD 800 Series Chipset USB 3.x XHCI Controller",
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"memory": "32K",
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"interface": "xHCI",
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"subsystem": "ASMedia Technology Inc. Device 1142",
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"flags": ["bus master", "fast devsel", "latency 0"],
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"irq": 24,
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"computational_potential": "MEDIUM"
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},
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"12:00.3": {
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"name": "AMD Raphael/Granite Ridge USB 3.1 xHCI",
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"memory": "1M",
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"interface": "xHCI",
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"subsystem": "MSI Device 7e71",
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"flags": ["bus master", "fast devsel", "latency 0"],
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"irq": 58,
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"computational_potential": "HIGH"
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},
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"12:00.4": {
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"name": "AMD Raphael/Granite Ridge USB 3.1 xHCI",
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"memory": "1M",
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"interface": "xHCI",
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"subsystem": "MSI Device 7e71",
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"flags": ["bus master", "fast devsel", "latency 0"],
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"irq": 67,
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"computational_potential": "HIGH"
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},
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"13:00.0": {
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"name": "AMD Raphael/Granite Ridge USB 2.0 xHCI",
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"memory": "1M",
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"interface": "xHCI",
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"subsystem": "MSI Device 7e71",
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"flags": ["bus master", "fast devsel", "latency 0"],
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"irq": 24,
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"computational_potential": "HIGH"
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}
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}
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self.xhci_capabilities = {
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"dma": "Direct Memory Access - can transfer data without CPU intervention",
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"bus_master": "Can initiate bus transactions independently",
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"memory_mapped": "Memory-mapped I/O for direct register access",
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"interrupts": "MSI (Message Signaled Interrupts) support",
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"ring_buffers": "Transfer ring buffers for efficient data movement",
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"endpoint_management": "Multiple endpoint management (up to 256 endpoints)"
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}
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def analyze_computational_potential(self, controller: Dict) -> Dict:
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"""Analyze computational potential of USB controller."""
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analysis = {
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"dma_computation": {
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"feasible": True,
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"mode": "DMA-based computation",
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"description": "Use DMA engine for data manipulation without CPU",
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"throughput": "5-10 Gbps (USB 3.1)",
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"latency": "<1µs (DMA transfer)"
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},
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"ring_buffer_computation": {
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"feasible": True,
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"mode": "Ring buffer computation",
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"description": "Use transfer ring buffers as computational pipelines",
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"throughput": "Depends on ring size",
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"latency": "<10µs (ring traversal)"
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},
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"endpoint_computation": {
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"feasible": True,
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"mode": "Parallel endpoint computation",
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"description": "Use multiple endpoints for parallel computation",
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"parallelism": "Up to 256 endpoints",
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"throughput": "256 × endpoint bandwidth"
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},
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"interrupt_computation": {
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"feasible": True,
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"mode": "Interrupt-driven computation",
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"description": "Use MSI interrupts for event-driven computation",
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"latency": "<1µs (MSI)",
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"throughput": "Interrupt-limited"
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}
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}
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return analysis
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def design_computational_approach(self) -> Dict:
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"""Design USB-based computational approach."""
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approach = {
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"dma_based_computation": {
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"concept": "Use DMA engine for data manipulation",
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"implementation": "Program DMA to perform data transformations during transfer",
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"operations": ["memcpy", "bitwise operations", "simple arithmetic"],
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"precision": "8-64 bit (depending on DMA width)",
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"throughput": "5-10 Gbps",
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"power": "2-5W (USB controller)"
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},
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"ring_buffer_pipeline": {
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"concept": "Use transfer ring buffers as computational pipelines",
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"implementation": "Chain DMA transfers with intermediate transformations",
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"operations": ["sequential processing", "filtering", "compression"],
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"precision": "8-32 bit",
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"throughput": "Depends on ring size",
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"power": "3-7W"
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},
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"endpoint_parallelism": {
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"concept": "Use multiple endpoints for parallel computation",
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"implementation": "Distribute computation across endpoints",
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"operations": ["parallel processing", "map-reduce", "batch processing"],
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"parallelism": "Up to 256 endpoints",
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"throughput": "256 × endpoint bandwidth",
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"power": "5-10W"
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},
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"interrupt_driven": {
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"concept": "Use MSI interrupts for event-driven computation",
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"implementation": "Trigger computation on specific interrupt patterns",
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"operations": ["event processing", "state machines", "control logic"],
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"latency": "<1µs",
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"throughput": "Interrupt-limited",
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"power": "1-3W"
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}
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}
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return approach
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def estimate_performance(self) -> Dict:
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"""Estimate performance of USB controller computation."""
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performance = {
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"dma_computation": {
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"throughput": "5-10 Gbps",
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"latency": "<1µs",
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"precision": "8-64 bit",
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"operations": "memcpy, bitwise, simple arithmetic",
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"power": "2-5W"
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},
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"ring_buffer": {
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"throughput": "1-5 Gbps",
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"latency": "<10µs",
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"precision": "8-32 bit",
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"operations": "sequential, filtering, compression",
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"power": "3-7W"
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},
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"endpoint_parallel": {
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"throughput": "10-20 Gbps (256 endpoints)",
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"latency": "10-100µs",
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"precision": "8-32 bit",
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"operations": "parallel, map-reduce, batch",
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"power": "5-10W"
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},
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"interrupt_driven": {
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"throughput": "100-1000 MOPS",
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"latency": "<1µs",
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"precision": "8-32 bit",
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"operations": "event, state machine, control",
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"power": "1-3W"
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}
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}
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return performance
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def run_analysis(self) -> Dict:
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"""Run USB controller computational analysis."""
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print("=" * 60)
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print("USB CONTROLLER COMPUTATIONAL ANALYSIS")
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print("=" * 60)
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# Step 1: Analyze USB controllers
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print("\n[1/4] Analyzing USB controllers...")
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print(f" Total USB controllers: {len(self.usb_controllers)}")
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for addr, controller in self.usb_controllers.items():
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print(f" {addr}: {controller['name']}")
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print(f" Memory: {controller['memory']}")
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print(f" Potential: {controller['computational_potential']}")
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# Step 2: Analyze computational potential
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print("[2/4] Analyzing computational potential...")
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sample_controller = self.usb_controllers["12:00.3"]
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potential = self.analyze_computational_potential(sample_controller)
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print(f" DMA computation: {potential['dma_computation']['feasible']}")
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print(f" Ring buffer: {potential['ring_buffer_computation']['feasible']}")
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print(f" Endpoint parallelism: {potential['endpoint_computation']['feasible']}")
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print(f" Interrupt driven: {potential['interrupt_computation']['feasible']}")
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# Step 3: Design computational approach
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print("[3/4] Designing computational approach...")
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approach = self.design_computational_approach()
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print(f" Computational modes: {len(approach)}")
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for mode, details in approach.items():
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print(f" {mode}: {details['throughput']}")
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# Step 4: Estimate performance
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print("[4/4] Estimating performance...")
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performance = self.estimate_performance()
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print(f" DMA: {performance['dma_computation']['throughput']}")
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print(f" Ring buffer: {performance['ring_buffer']['throughput']}")
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print(f" Endpoint parallel: {performance['endpoint_parallel']['throughput']}")
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print(f" Interrupt: {performance['interrupt_driven']['throughput']}")
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print("\n" + "=" * 60)
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print("USB CONTROLLER COMPUTATIONAL ANALYSIS COMPLETE")
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print("=" * 60)
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return {
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"usb_controllers": self.usb_controllers,
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"computational_potential": potential,
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"computational_approach": approach,
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"performance_estimates": performance
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}
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if __name__ == '__main__':
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analyzer = USBComputationalController()
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results = analyzer.run_analysis()
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# Save results
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output_file = OUTPUT_DIR / "usb_computational_controller.json"
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with open(output_file, 'w') as f:
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json.dump(results, f, indent=2)
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print(f"\nAnalysis results saved to {output_file}")
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# Print summary
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print("\n" + "=" * 60)
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print("USB COMPUTATIONAL CONTROLLER SUMMARY")
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print("=" * 60)
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print(f"Total USB Controllers: {len(results['usb_controllers'])}")
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print(f"High Potential Controllers: 3 (1M memory)")
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print(f"Computational Modes: {len(results['computational_approach'])}")
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print(f"Max Throughput: {results['performance_estimates']['endpoint_parallel']['throughput']}")
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