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2aef54d052
Lean: update Semantics modules, add new numerics/physics data files Hardware: update FPGA bitstreams (tangnano9k_uart_loopback) Infra: k3s-flake tests, netcup-vps configuration, VCN compute substrate Docs: ARCHITECTURE, specs, citation updates
19 lines
697 B
Text
19 lines
697 B
Text
// Tang Nano 9K UART test constraints
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// Board: Sipeed Tang Nano 9K (BL702 revision)
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// FPGA pin 17 = TX to host (via BL702), pin 18 = RX from host
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IO_LOC "clk" 52;
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IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
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IO_LOC "uart_tx" 17;
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IO_PORT "uart_tx" IO_TYPE=LVCMOS33 DRIVE=8;
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IO_LOC "led[0]" 10;
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IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[1]" 11;
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IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[2]" 13;
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IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[3]" 14;
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IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[4]" 15;
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IO_PORT "led[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[5]" 16;
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IO_PORT "led[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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