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https://github.com/allaunthefox/Research-Stack.git
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ba203ca971
Ported from ScaleSpaceSynth (WebGPU particle simulator): - 64×64×64 spatial hash, 32 particles/cell, lock-free insertion - Curl noise: divergence-free 3D turbulence - Pairwise forces: attractive (ratio>0.15) + repulsive (ratio<=0.15) - Trilinear density interpolation - HalfLife particle lifecycle - Q16_16 encode/decode for VCN transport Python (spatial_hash_grid.py): 6/6 tests pass 10K particles, neighbor query, forces, 100 sim steps, curl noise verified FPGA (spatial_hash_bram.v): 16×16×16 grid, dual-port BRAM, 27-cycle neighbor scan Density → voltage mode selector (STORE/COMPUTE/APPROX/MORPHIC) Integrated into research_stack_top.v Same pattern as ScaleSpaceSynth GPU: GPU: atomicAdd for lock-free cell assignment FPGA: BRAM read-modify-write for cell assignment Ray: content-addressed ObjectRef for lock-free reads All: partition space → compute density → find structure at multiple scales
45 lines
1 KiB
Bash
45 lines
1 KiB
Bash
#!/usr/bin/env bash
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set -euo pipefail
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cd "$(dirname "$0")"
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TOP="research_stack_top"
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CST="research_stack_tangnano9k.cst"
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JSON="research_stack_top.json"
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PNR="research_stack_top_pnr.json"
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FS="research_stack_top.fs"
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DEVICE="GW1NR-LV9QN88PC6/I5"
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FAMILY="GW1N-9C"
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FREQ=27
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Q16_V="../../5-Applications/out/verilog/q16_lut_core.v"
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echo "=== Synthesis ==="
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yosys -p "
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read_verilog -sv \
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${Q16_V} \
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blitter_memory_map.v \
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voltage_mode_controller.v \
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scale_space_bram.v \
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highs_pivot_accelerator.v \
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fractal_box_counter.v \
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fractal_fd_selector.v \
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spatial_hash_bram.v \
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spatial_hash_selector.v \
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Blitter6502OISC_small.v \
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research_stack_top.v;
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synth_gowin -top ${TOP} -json ${JSON};
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stat
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"
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echo ""
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echo "=== Place & Route ==="
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nextpnr-himbaechel --device "${DEVICE}" --json "${JSON}" --write "${PNR}" \
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--freq "${FREQ}" --vopt "family=${FAMILY}" --vopt "cst=${CST}"
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echo ""
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echo "=== Bitstream ==="
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gowin_pack -d "${FAMILY}" -o "${FS}" "${PNR}"
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echo ""
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echo "=== Done: ${FS} ==="
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ls -lh "${FS}"
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