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58b95a9814
Paper: 'Ultra-fast computation of fractal dimension for RGB images' (Pattern Analysis and Applications, 2025) Python (fractal_dimension.py): - DBC algorithm with numpy vectorization (29x faster than scalar) - fd_compress_hint: FD → voltage mode (STORE/COMPUTE/APPROX/MORPHIC) - 7/7 tests pass (Sierpinski, random, gradient, checkerboard, fBm, constant, RGB) - Q16_16 integer arithmetic internally FPGA (fractal_box_counter.v + fractal_fd_selector.v): - 5-state FSM: IDLE → COLLECT → FINALIZE → STORE_LOG → REGRESS → DONE - 8 power-of-two scales (2, 4, 8, ..., 256) - Linear regression via Q16_16 64-bit arithmetic - FD clamped to [1.0, 3.0] in Q16_16 - Selector: FD < 2.3 → STORE, < 2.6 → COMPUTE, < 2.9 → APPROX, >= 2.9 → MORPHIC - Integrated into research_stack_top.v FD drives adaptive compression: Low FD (smooth) → STORE mode (minimal compression) High FD (rough) → MORPHIC mode (aggressive compression)
65 lines
2 KiB
Verilog
65 lines
2 KiB
Verilog
`timescale 1ns / 1ps
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// Fractal Dimension → Voltage Mode Selector
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// Maps computed fractal dimension (Q16_16) to a 2-bit voltage mode for the
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// voltage_mode_controller.
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//
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// FD < 2.3 → voltage_mode = 0 (STORE)
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// FD < 2.6 → voltage_mode = 1 (COMPUTE)
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// FD < 2.9 → voltage_mode = 2 (APPROX)
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// FD >= 2.9 → voltage_mode = 3 (MORPHIC)
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//
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// Thresholds in Q16_16:
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// 2.3 = 2 + 0.3 = 0x0002_4CCD (131072 + 19661 = 150733)
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// 2.6 = 2 + 0.6 = 0x0002_999A (131072 + 39322 = 170394)
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// 2.9 = 2 + 0.9 = 0x0002_E666 (131072 + 58982 = 190054)
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module fractal_fd_selector (
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input wire clk,
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input wire rst_n,
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input wire [31:0] fd_q16, // fractal dimension in Q16_16
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input wire fd_valid, // fd_q16 is valid
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output reg [1:0] voltage_mode, // 0=STORE, 1=COMPUTE, 2=APPROX, 3=MORPHIC
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output reg mode_valid // mode output is valid
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);
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// Threshold constants in Q16_16
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localparam [31:0] THRESH_2_3 = 32'h0002_4CCD; // 2.3
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localparam [31:0] THRESH_2_6 = 32'h0002_999A; // 2.6
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localparam [31:0] THRESH_2_9 = 32'h0002_E666; // 2.9
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// Mode definitions (match voltage_mode_controller)
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localparam MODE_STORE = 2'b00;
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localparam MODE_COMPUTE = 2'b01;
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localparam MODE_APPROX = 2'b10;
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localparam MODE_MORPHIC = 2'b11;
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// Combinational mode selection
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reg [1:0] mode_next;
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always @(*) begin
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if (fd_q16 < THRESH_2_3)
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mode_next = MODE_STORE;
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else if (fd_q16 < THRESH_2_6)
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mode_next = MODE_COMPUTE;
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else if (fd_q16 < THRESH_2_9)
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mode_next = MODE_APPROX;
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else
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mode_next = MODE_MORPHIC;
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end
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// Register output
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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voltage_mode <= MODE_STORE;
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mode_valid <= 1'b0;
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end else begin
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mode_valid <= 1'b0;
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if (fd_valid) begin
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voltage_mode <= mode_next;
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mode_valid <= 1'b1;
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end
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end
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end
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endmodule
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