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a3b298230b
Pipeline wiring: - vcn_compute_substrate.py: Delta+RLE → RS ECC → ChaCha20 now in live path - encode_braid_strand/crossing/mountain_merge accept key + compress params - New CLI: encode_enhanced/decode_enhanced for full pipeline - 67/67 tests pass FPGA synthesis: - q16_lut_core → Tang Nano 9K (GW1NR-9C) - 266 LUTs, 68 FFs, 2 DSPs, 1 BRAM - 3.4MB bitstream (q16_lut_top.fs) - Constraint file + build script + wrapper module
28 lines
725 B
Verilog
28 lines
725 B
Verilog
// Wrapper for q16_lut_core that maps valid to result[31]
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// This reduces the pin count to fit the Tang Nano 9K
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module q16_lut_top (
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input wire clk,
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input wire rst,
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input wire [2:0] op_select,
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input wire [15:0] a,
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input wire [15:0] b,
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output wire [31:0] result
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);
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wire [31:0] core_result;
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wire core_valid;
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q16_lut_core u_core (
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.clk (clk),
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.rst (rst),
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.op_select (op_select),
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.a (a),
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.b (b),
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.result (core_result),
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.valid (core_valid)
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);
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// Map valid into result[31] bit for external observation
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assign result = {core_valid, core_result[30:0]};
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endmodule
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