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270ef14e21
Blitter6502OISC_small.v: - Added uart_sent flag to prevent UART retransmission - Verified via Verilator: UART sends exactly one byte on halt - Test byte: 0xAA (recognizable pattern) research_stack_top.v: - Auto-start logic (100ms after reset, no button needed) - LED shows heartbeat when CPU running, register values on halt research_stack_tangnano9k.cst: - uart_tx=17, uart_rx=18 (matches Sparkle reference design) Simulation results (Verilator): - uart_test.v: 115 bytes in 300K cycles (continuous TX verified) - research_stack_top: UART fires after Blitter halt, 0xAA byte sent - LED pattern changes from IDLE to RUNNING to HALTED
40 lines
1.1 KiB
Verilog
40 lines
1.1 KiB
Verilog
// Minimal UART test: sends 'R' (0x52) continuously at 115200 baud
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// Verifies FT2232 channel B ↔ FPGA pin 18 connection
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module uart_test (
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input wire clk,
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output wire uart_tx,
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output wire [5:0] led
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);
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// 27MHz / 234 = 115384 baud
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localparam BAUD_DIV = 16'd233;
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localparam TEST_BYTE = 8'h52; // 'R' for Research Stack
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assign led = 6'b101010; // Pattern to confirm FPGA is alive
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reg [15:0] baud_cnt = 0;
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reg [3:0] bit_cnt = 0;
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reg [9:0] shift_reg = 10'b1111111111;
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reg tx_out = 1'b1;
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assign uart_tx = tx_out;
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always @(posedge clk) begin
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if (baud_cnt >= BAUD_DIV) begin
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baud_cnt <= 0;
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if (bit_cnt == 0) begin
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// Load start bit + data + stop bit
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shift_reg <= {1'b1, TEST_BYTE, 1'b0};
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bit_cnt <= 10;
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tx_out <= 1'b0; // Start bit
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end else begin
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tx_out <= shift_reg[0];
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shift_reg <= {1'b1, shift_reg[9:1]};
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bit_cnt <= bit_cnt - 1;
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end
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end else begin
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baud_cnt <= baud_cnt + 1;
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end
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end
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endmodule
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