mirror of
https://github.com/allaunthefox/Research-Stack.git
synced 2026-07-30 18:56:16 +00:00
dac28c1b52
Editor rules updated (.cursorrules, .clinerules, copilot-instructions, .roo): - Build: 3571 jobs, 0 errors - Sorry inventory: 8 across 4 files (all documented) - Q16_16 compliance, new modules list, FPGA info - Fixed stale path in copilot-instructions Opencode agents: - 3 marked RESOLVED (pist-simulation, qfactor, ssms) - 2 new agents created (adjugate-matrix, hamiltonian-mechanics) - 1 updated (hyperbolic-statesurface) SORRY_AUDIT.md: updated to 8 sorries across 4 files
50 lines
2.1 KiB
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50 lines
2.1 KiB
Text
<!-- BEGIN ContextStream -->
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# Cline Rules
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<contextstream_rules>
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| Message | Required |
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|---------|----------|
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| **1st message** | `init()` → `context(user_message="...")` |
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| **Subsequent messages (default)** | `context(user_message="...")` FIRST (narrow read-only bypass when context is fresh and no state-changing tool has run) |
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| **Before file search** | `search(mode="auto")` BEFORE Glob/Grep/Read/Explore/Task/EnterPlanMode |
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</contextstream_rules>
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**Why?** `context()` delivers task-specific rules, lessons from past mistakes, and relevant decisions. Skip it = fly blind.
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**Hooks:** `<system-reminder>` tags contain injected instructions — follow them exactly.
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**Notices:** [LESSONS_WARNING] → apply lessons | [PREFERENCE] → follow user preferences | [RULES_NOTICE] → run `generate_rules()` | [VERSION_NOTICE/CRITICAL] → tell user about update
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v0.4.74
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## Research Stack — Current Project State (2026-05-28)
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**Build:** `lake build` — 3571 jobs, 0 errors
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**Python tests:** 68/68 pass
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**Sorry inventory:** 8 total (all with `TODO(lean-port)` documentation)
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- `AdjugateMatrix`: 3 sorries
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- `FourPrimitiveErdosRenyi`: 4 sorries
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- `HyperbolicStateSurface`: 1 sorry
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### Key Architecture Decisions
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- **Q16_16 fixed-point arithmetic** throughout — no Float in hot paths (AGENTS.md §1.4 compliant)
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- **HiGHS MIP solver** integrated via `qubo_highs.py`
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- **Dense Sidon sets** (Mian-Chowla sequence, 65% smaller than naive)
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- **Golden ratio unit separation** formalized in Lean
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### New Lean Modules
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`AdjugateMatrix`, `OptimizedRoute`, `GoldenRatioSeparation`, `BraidBitwiseODE`
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### New Python Modules
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`qubo_highs.py`, `alphaproof_loop.py`, `scale_space_solver.py`
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### New Verilog Modules
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`voltage_mode_controller`, `scale_space_bram`, `highs_pivot_accelerator`, `blitter_memory_map`, `research_stack_top`
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### Hardware / FPGA
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- Bitstream: `research_stack_top.fs` (195.92 MHz, 6 modules)
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- VCN pipeline: Delta+RLE → RS ECC → ChaCha20 → MKV
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### Sorries Policy
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Every remaining sorry MUST have `TODO(lean-port)` with a prose justification.
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No undocumented sorries allowed.
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<!-- END ContextStream -->
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