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27 lines
539 B
Verilog
27 lines
539 B
Verilog
module MetaManifoldProver #(
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parameter DATA_WIDTH = 1
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)(
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input wire clk,
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input wire rst_n,
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// Status LEDs
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output reg busy,
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output reg done
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);
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// Simple counter for testing
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reg [3:0] counter;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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counter <= 4'd0;
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busy <= 1'b0;
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done <= 1'b0;
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end else begin
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counter <= counter + 1'b1;
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busy <= counter[0];
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done <= counter[1];
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end
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end
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endmodule
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