mirror of
https://github.com/allaunthefox/Research-Stack.git
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209 lines
8.7 KiB
Python
209 lines
8.7 KiB
Python
#!/usr/bin/env python3
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"""
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PCIe Controller Computational Repurposing
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Analyzes PCIe controller for general-purpose computation capabilities.
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"""
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import json
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from pathlib import Path
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from typing import Dict, List, Optional
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# Paths
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OUTPUT_DIR = Path("/home/allaun/Documents/Research Stack/out")
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class PCIeComputationalController:
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"""Analyzes PCIe controller for general computation."""
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def __init__(self):
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self.pcie_controller = {
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"device": "AMD 600 Series Chipset PCIe Switch Upstream Port",
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"address": "03:00.0",
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"subsystem": "ASMedia Technology Inc. Device 3328",
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"flags": ["bus master", "fast devsel", "latency 0"],
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"irq": 24,
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"iommu_group": 14,
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"bus": "primary=03, secondary=04, subordinate=11, sec-latency=0",
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"io_bridge": "e000-efff [size=4K] [16-bit]",
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"memory_bridge": "f5200000-f58fffff [size=7M] [32-bit]",
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"computational_potential": "HIGH (PCIe switching and routing)"
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}
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self.pcie_capabilities = {
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"bus_master": "Can initiate bus transactions independently",
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"memory_mapped": "Memory-mapped I/O for direct register access",
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"dma": "Direct Memory Access support",
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"switching": "PCIe switching between buses",
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"routing": "PCIe routing between devices",
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"bandwidth": "PCIe bandwidth (32-64 GB/s for PCIe 4.0 x16)"
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}
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def analyze_computational_potential(self) -> Dict:
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"""Analyze computational potential of PCIe controller."""
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analysis = {
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"pcie_switching": {
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"feasible": True,
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"mode": "PCIe switching computation",
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"description": "Use PCIe switching for computational routing",
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"throughput": "PCIe bandwidth limited (32-64 GB/s)",
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"latency": "100-1000ns (switch traversal)",
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"power": "5-15W (PCIe controller)"
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},
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"pcie_routing": {
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"feasible": True,
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"mode": "PCIe routing computation",
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"description": "Use PCIe routing for computational paths",
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"throughput": "PCIe bandwidth limited",
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"latency": "100-1000ns (routing)",
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"power": "5-15W"
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},
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"pcie_dma": {
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"feasible": True,
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"mode": "PCIe DMA computation",
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"description": "Use PCIe DMA for memory-based computation",
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"throughput": "PCIe bandwidth limited",
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"latency": "<100ns (DMA)",
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"power": "10-20W"
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}
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}
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return analysis
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def design_computational_approach(self) -> Dict:
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"""Design PCIe-based computational approach."""
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approach = {
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"pcie_switching_computation": {
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"concept": "Use PCIe switching for computation",
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"implementation": "Switch PCIe lanes for computational routing",
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"operations": ["lane switching", "path computation", "switch matrix"],
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"throughput": "PCIe bandwidth limited (32-64 GB/s)",
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"latency": "100-1000ns (switch traversal)",
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"power": "5-15W"
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},
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"pcie_routing_computation": {
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"concept": "Use PCIe routing for computation",
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"implementation": "Route PCIe packets through specific paths",
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"operations": ["packet routing", "path optimization", "flow control"],
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"throughput": "PCIe bandwidth limited",
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"latency": "100-1000ns (routing)",
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"power": "5-15W"
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},
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"pcie_dma_computation": {
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"concept": "Use PCIe DMA for computation",
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"implementation": "Use PCIe DMA for memory-based computation",
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"operations": ["memory access", "data transformation", "scatter-gather"],
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"throughput": "PCIe bandwidth limited (32-64 GB/s)",
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"latency": "<100ns (DMA)",
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"power": "10-20W"
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},
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"pcie_packet_computation": {
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"concept": "Use PCIe packets for computation",
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"implementation": "Manipulate PCIe packet headers/payloads",
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"operations": ["header manipulation", "payload transformation", "TLP processing"],
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"throughput": "PCIe bandwidth limited",
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"latency": "100-1000ns (packet processing)",
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"power": "5-15W"
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}
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}
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return approach
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def estimate_performance(self) -> Dict:
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"""Estimate performance of PCIe controller computation."""
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performance = {
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"pcie_switching": {
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"throughput": "PCIe bandwidth limited (32-64 GB/s)",
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"latency": "100-1000ns (switch traversal)",
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"precision": "PCIe lane",
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"operations": "lane switching",
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"power": "5-15W"
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},
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"pcie_routing": {
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"throughput": "PCIe bandwidth limited (32-64 GB/s)",
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"latency": "100-1000ns (routing)",
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"precision": "PCIe packet",
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"operations": "packet routing",
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"power": "5-15W"
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},
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"pcie_dma": {
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"throughput": "PCIe bandwidth limited (32-64 GB/s)",
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"latency": "<100ns (DMA)",
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"precision": "PCIe DMA",
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"operations": "memory access",
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"power": "10-20W"
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},
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"pcie_packet": {
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"throughput": "PCIe bandwidth limited (32-64 GB/s)",
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"latency": "100-1000ns (packet processing)",
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"precision": "PCIe TLP",
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"operations": "packet processing",
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"power": "5-15W"
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}
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}
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return performance
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def run_analysis(self) -> Dict:
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"""Run PCIe controller computational analysis."""
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print("=" * 60)
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print("PCIe CONTROLLER COMPUTATIONAL ANALYSIS")
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print("=" * 60)
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# Step 1: Analyze PCIe controller
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print("\n[1/4] Analyzing PCIe controller...")
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print(f" Device: {self.pcie_controller['device']}")
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print(f" Address: {self.pcie_controller['address']}")
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print(f" Memory Bridge: {self.pcie_controller['memory_bridge']}")
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print(f" Computational Potential: {self.pcie_controller['computational_potential']}")
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# Step 2: Analyze computational potential
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print("[2/4] Analyzing computational potential...")
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potential = self.analyze_computational_potential()
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print(f" PCIe Switching: {potential['pcie_switching']['feasible']}")
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print(f" PCIe Routing: {potential['pcie_routing']['feasible']}")
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print(f" PCIe DMA: {potential['pcie_dma']['feasible']}")
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# Step 3: Design computational approach
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print("[3/4] Designing computational approach...")
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approach = self.design_computational_approach()
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print(f" Computational modes: {len(approach)}")
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for mode, details in approach.items():
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print(f" {mode}: {details['throughput']}")
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# Step 4: Estimate performance
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print("[4/4] Estimating performance...")
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performance = self.estimate_performance()
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print(f" PCIe Switching: {performance['pcie_switching']['throughput']}")
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print(f" PCIe Routing: {performance['pcie_routing']['throughput']}")
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print(f" PCIe DMA: {performance['pcie_dma']['throughput']}")
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print(f" PCIe Packet: {performance['pcie_packet']['throughput']}")
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print("\n" + "=" * 60)
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print("PCIe CONTROLLER COMPUTATIONAL ANALYSIS COMPLETE")
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print("=" * 60)
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return {
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"pcie_controller": self.pcie_controller,
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"computational_potential": potential,
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"computational_approach": approach,
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"performance_estimates": performance
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}
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if __name__ == '__main__':
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analyzer = PCIeComputationalController()
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results = analyzer.run_analysis()
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# Save results
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output_file = OUTPUT_DIR / "pcie_computational_controller.json"
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with open(output_file, 'w') as f:
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json.dump(results, f, indent=2)
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print(f"\nAnalysis results saved to {output_file}")
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# Print summary
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print("\n" + "=" * 60)
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print("PCIe COMPUTATIONAL CONTROLLER SUMMARY")
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print("=" * 60)
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print(f"Device: {results['pcie_controller']['device']}")
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print(f"Memory Bridge: {results['pcie_controller']['memory_bridge']}")
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print(f"Computational Potential: {results['pcie_controller']['computational_potential']}")
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print(f"Max Throughput: {results['performance_estimates']['pcie_switching']['throughput']}")
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