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28 lines
1 KiB
Verilog
28 lines
1 KiB
Verilog
// Auto-generated from Lean: Semantics.Hardware.TangNano9K.emitGenome18Address
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// Source of truth: Semantics.Genome18.addr
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// Theorem: verilogAddr_eq_addr (forall g, verilogAddr g = g.addr)
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// Theorem: addr_injective (Function.Injective addr)
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// Theorem: addr_range (addr < 262144)
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//
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// DO NOT EDIT BY HAND. Regenerate via: lake exe tangnano9k_emitter
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`timescale 1ns / 1ps
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module Genome18Address (
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input wire [2:0] muBin,
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input wire [2:0] rhoBin,
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input wire [2:0] cBin,
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input wire [2:0] mBin,
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input wire [2:0] neBin,
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input wire [2:0] sigmaBin,
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output wire [17:0] addr
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);
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// Each bin is 3-bit (0..7). The weights are exact powers of two
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// so synthesis maps them to shifts; no multiplier DSP needed.
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assign addr = ({15'd0, muBin} * 18'd32768) +
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({15'd0, rhoBin} * 18'd4096) +
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({15'd0, cBin} * 18'd512) +
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({15'd0, mBin} * 18'd64) +
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({15'd0, neBin} * 18'd8) +
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{12'd0, sigmaBin};
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endmodule
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