Research-Stack/6-Documentation/tiddlywiki-local/wiki/tiddlers/TMDS Timing-Plane Invariants.tid
Brandon Schneider 453a366949 collapse: prover orchestration layers, FAMM verilator harness, swarm topological prober, spec sheets, virtual FPGA system tests, merge conflict resolution
- Prover-Integrated Orchestration Layers (L0-L3): Goedel-Prover-V2 watchdog, BFS-Prover-V2 swarm consensus, bf4prover topology adaptation
- FAMM Verilator benchmark: uniform vs preshaped delay comparison (4.4x speedup)
- Swarm topological device prober: 11 agents probing traces, caps, delays, errors, vias, PDN
- Spec sheet puller: 10 components with key params and topological relevance
- Virtual FPGA system tests: 6/6 passed, 134K ops/s throughput
- Fixed merge conflicts in AI-Newton test_experiment.ipynb
2026-05-06 23:42:01 -05:00

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created: 20260506151000000
modified: 20260506151000000
tags: ResearchStack Hardware HDMI SearchProtocol Candidate
title: TMDS Timing-Plane Invariants
type: text/vnd.tiddlywiki
! TMDS Timing-Plane Invariants
The HDMI/TMDS timing layer treated as a deterministic clock-law plane for
state packets and witness routing.
!! Why It Matters
This splits [[HDMI Compute Fabric]] into a concrete timing primitive: the
transport is not just pixels, it is ordered symbols with cadence, blanking,
and synchronization structure.
!! Evidence
* Source: `shared-data/data/ingested/chatgpt/hdmi_as_computation_fabric.graphml:8`
* Source: `shared-data/data/ingested/chatgpt/hdmi_as_computation_fabric_graph_edges.jsonl:2`
* Source: `shared-data/data/ingested/chatgpt/hdmi_as_computation_fabric_graph_edges.jsonl:8`
* Lane: [[Deep Mining Pass 2026-05-06]]
!! Links
* [[HDMI Compute Fabric]]
* [[Virtual Display Blitter Compute Surface]]
* [[Raster Lookup Unit]]