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50 lines
1.8 KiB
Text
50 lines
1.8 KiB
Text
import Semantics.PBACSSignal
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namespace Semantics.PBACSSignal
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open Semantics.PISTMachine
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/-! # PBACS REV3 — Verilog Equivalence
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Formal equivalence proof between Lean 4 specification and Verilog HDL.
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Anchored to: scripts/pbacs_rev3_hdl.v
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-/
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/-- Bit-accurate hardware simulation of the Verilog always block. -/
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def verilogStep (s : State) (v_t : Int32) : State :=
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let phiNext := s.phi + 106070
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let theta_t : Int32 := if phiNext >= 0x80000000 then 32768 else -32768
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-- Step 3 & 4: Decision logic matching Verilog `if ((sample_in + error) > theta_t)`
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let b_t := if theta_t < v_t + s.error then true else false
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let e_next := v_t + s.error - (if b_t then theta_t else 0)
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-- Step 5-8: Tension matching Verilog `(tension * 921 + stress * 103) >> 10`
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let stress := (e_next).abs
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let tensionNext := (s.tension * 921 + stress.toUInt32 * 103) / 1024
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let phaseNext :=
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if tensionNext > 50000 then Phase.seismic
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else if tensionNext > 10000 then Phase.drift
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else Phase.grounded
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-- L5: Update bracket (Constraint-preserving interval)
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let v_q := _root_.Semantics.Q16_16.ofInt v_t.toInt
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let newBracket := Semantics.BracketedCalculus.BracketedDIAT.encode
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(s.bracket.lower + v_q - _root_.Semantics.Q16_16.epsilon)
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(v_q)
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(s.bracket.upper + v_q + _root_.Semantics.Q16_16.epsilon)
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s.bracket.scale
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{ phi := phiNext
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, error := e_next
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, tension := tensionNext
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, phase := phaseNext
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, lastSymbol := b_t
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, bracket := newBracket }
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/-- Identity Equivalence Theorem.
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Synchronizes the hardware implementation with its formal model. -/
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theorem hardwareEquivalence (s : State) (v_t : Int32) :
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State.update s v_t = verilogStep s v_t := rfl
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end Semantics.PBACSSignal
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