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https://github.com/allaunthefox/Research-Stack.git
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Paper: 'Ultra-fast computation of fractal dimension for RGB images' (Pattern Analysis and Applications, 2025) Python (fractal_dimension.py): - DBC algorithm with numpy vectorization (29x faster than scalar) - fd_compress_hint: FD → voltage mode (STORE/COMPUTE/APPROX/MORPHIC) - 7/7 tests pass (Sierpinski, random, gradient, checkerboard, fBm, constant, RGB) - Q16_16 integer arithmetic internally FPGA (fractal_box_counter.v + fractal_fd_selector.v): - 5-state FSM: IDLE → COLLECT → FINALIZE → STORE_LOG → REGRESS → DONE - 8 power-of-two scales (2, 4, 8, ..., 256) - Linear regression via Q16_16 64-bit arithmetic - FD clamped to [1.0, 3.0] in Q16_16 - Selector: FD < 2.3 → STORE, < 2.6 → COMPUTE, < 2.9 → APPROX, >= 2.9 → MORPHIC - Integrated into research_stack_top.v FD drives adaptive compression: Low FD (smooth) → STORE mode (minimal compression) High FD (rough) → MORPHIC mode (aggressive compression)
43 lines
985 B
Bash
Executable file
43 lines
985 B
Bash
Executable file
#!/usr/bin/env bash
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set -euo pipefail
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cd "$(dirname "$0")"
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TOP="research_stack_top"
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CST="research_stack_tangnano9k.cst"
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JSON="research_stack_top.json"
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PNR="research_stack_top_pnr.json"
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FS="research_stack_top.fs"
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DEVICE="GW1NR-LV9QN88PC6/I5"
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FAMILY="GW1N-9C"
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FREQ=27
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Q16_V="../../5-Applications/out/verilog/q16_lut_core.v"
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echo "=== Synthesis ==="
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yosys -p "
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read_verilog -sv \
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${Q16_V} \
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blitter_memory_map.v \
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voltage_mode_controller.v \
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scale_space_bram.v \
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highs_pivot_accelerator.v \
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fractal_box_counter.v \
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fractal_fd_selector.v \
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Blitter6502OISC_small.v \
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research_stack_top.v;
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synth_gowin -top ${TOP} -json ${JSON};
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stat
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"
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echo ""
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echo "=== Place & Route ==="
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nextpnr-himbaechel --device "${DEVICE}" --json "${JSON}" --write "${PNR}" \
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--freq "${FREQ}" --vopt "family=${FAMILY}" --vopt "cst=${CST}"
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echo ""
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echo "=== Bitstream ==="
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gowin_pack -d "${FAMILY}" -o "${FS}" "${PNR}"
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echo ""
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echo "=== Done: ${FS} ==="
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ls -lh "${FS}"
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