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e5fb0a5f4d
Lean: update Semantics modules, add new numerics/physics data files Hardware: update FPGA bitstreams (tangnano9k_uart_loopback) Infra: k3s-flake tests, netcup-vps configuration, VCN compute substrate Docs: ARCHITECTURE, specs, citation updates
88 lines
2.9 KiB
Verilog
88 lines
2.9 KiB
Verilog
// Q16_16 LUT Core — Fixed-Point Arithmetic Unit
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// Stub based on interface from q16_lut_top.v
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// 8 operations, 2-stage pipeline
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// Original was generated by Lean Semantics tooling and exists as .json netlist.
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// This stub provides the same interface for unified builds.
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//
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// op_select encoding:
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// 000 = add (a + b)
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// 001 = sub (a - b)
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// 010 = mul (a * b, Q16_16 product)
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// 011 = div (a / b, Q16_16 quotient)
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// 100 = sqrt (sqrt(a))
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// 101 = abs (|a|)
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// 110 = min (min(a,b))
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// 111 = max (max(a,b))
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`timescale 1ns / 1ps
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module q16_lut_core (
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input wire clk,
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input wire rst,
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input wire [2:0] op_select,
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input wire [15:0] a,
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input wire [15:0] b,
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output reg [31:0] result,
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output reg valid
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);
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// Pipeline stage 1: decode and latch inputs
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reg [2:0] op_reg;
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reg [15:0] a_reg;
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reg [15:0] b_reg;
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reg valid_s1;
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// Pipeline stage 2: execute
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reg [31:0] result_s2;
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reg valid_s2;
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// Intermediate computation (combinational)
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reg [31:0] compute_result;
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always @(*) begin
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case (op_reg)
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3'b000: compute_result = {16'd0, a_reg} + {16'd0, b_reg}; // add
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3'b001: compute_result = {16'd0, a_reg} - {16'd0, b_reg}; // sub
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3'b010: compute_result = (a_reg * b_reg); // mul (simplified)
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3'b011: begin // div
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if (b_reg != 16'd0)
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compute_result = ({16'd0, a_reg} << 16) / {16'd0, b_reg};
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else
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compute_result = 32'h7FFFFFFF; // saturate
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end
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3'b100: compute_result = {16'd0, a_reg}; // sqrt (passthrough stub)
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3'b101: compute_result = a_reg[15] ? {16'd0, (~a_reg + 16'd1)} : {16'd0, a_reg}; // abs
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3'b110: compute_result = (a_reg <= b_reg) ? {16'd0, a_reg} : {16'd0, b_reg}; // min
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3'b111: compute_result = (a_reg >= b_reg) ? {16'd0, a_reg} : {16'd0, b_reg}; // max
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endcase
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end
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// Pipeline registers
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always @(posedge clk) begin
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if (rst) begin
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op_reg <= 3'd0;
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a_reg <= 16'd0;
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b_reg <= 16'd0;
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valid_s1 <= 1'b0;
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result_s2 <= 32'd0;
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valid_s2 <= 1'b0;
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result <= 32'd0;
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valid <= 1'b0;
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end else begin
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// Stage 1: latch inputs
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op_reg <= op_select;
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a_reg <= a;
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b_reg <= b;
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valid_s1 <= 1'b1; // always valid after first cycle
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// Stage 2: compute
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result_s2 <= compute_result;
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valid_s2 <= valid_s1;
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// Output
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result <= result_s2;
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valid <= valid_s2;
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end
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end
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endmodule
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