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docs(research): HCMR × chiral CRT multiplexer — performance model
HCMR (HardwareContentionMarkov.lean, Research Stack, 0 sorries) provides
the hardware performance model for the chiral CRT multiplexer.
Connection:
- Markov self-loop probability = Sidon collision rate
- Mixing rate = multiplexer throughput
- Cache hierarchy (L1→L2→L3→DRAM) = TreeBraid hierarchy (leaf→node→root)
- COUCH gate = contention filter (rejects high self-loop configs)
HCMR measured self-loop probabilities:
SUBLEQ (word): 0.823 (82.3% contention)
CL AVX-512: 0.885 (88.5% contention)
Ring dispatch: 0.0 (0% contention — perfectly Sidon-orthogonal)
Throughput formula: base_rate × (1 - self_loop_prob)
= base_rate × Sidon_pass_rate
This predicts multiplexer performance:
Ring dispatch (q >> 1): 4/4 channels usable (100% Sidon)
Word SUBLEQ (q ≈ 1.5): 0.7/4 channels usable (18% Sidon)
CL AVX-512 (q ≈ 1.0): 0.5/4 channels usable (12% Sidon)
Confirms q-profile sweep finding: q > 1 = 100% Sidon = ring dispatch regime.
Port plan: HCMR → formal/SilverSight/HCMR/ following pipeline-math
5-file pattern, with capstone theorem connecting Sidon pass rate
to HCMR throughput.
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2026-07-04 19:46:15 +00:00 |
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