C: type_mismatch test adjusted for C port (returns default on type error)
C++: variant comparison fixed with val_i/val_b helpers, all tests use proper accessors
Go: added go.mod to repo so go test works from any directory
Octave: test now uses addpath to find AVM class
Test harnesses added for all remaining AVM ISA ports:
- C (9 tests): arithmetic, saturation, comparison, overflow, control flow, locals
- C++ (9 tests): same test suite with std::optional-based error handling
- Scala (9 tests): functional style with Option return
- Fortran (4 tests): add, div, saturation, control flow (minimal Fortran test)
- Octave/MATLAB (4 tests): basic operations test
Milestone: 10/12 ports have test harnesses. Coq still pending.
Python port rewritten to match spec:
- Added Q0_16, PUSH_Q0, PUSH_BOOL as separate opcodes
- Added V6 comparison (lt_q16_v6)
- Added floor division (Lean Int.ediv)
- Added stack depth limit (AVM_MAX_STACK = 1024)
- Added type checking in exec_prim
- All 10 tests passing
Go AVM port: added test_avm_test.go with 8 test cases
Milestone: Python → ✅, Go → 🔄
Ports three Research Stack RRC gates into formal/SilverSight/RRC/ using the existing CoreFormalism braid and Q16_16 surfaces.
Adds a Lean ↔ C ↔ Python Q16_16 roundtrip test:
- c/q16_canonical.c: canonical saturating Q16_16 C library
- exe/Q16_16Roundtrip.lean: Lake extern_lib linked executable
- tests/test_q16_roundtrip.py: Python ↔ C harness (revived from quarantine)
Updates lakefile.lean with q16-roundtrip executable and extern_lib q16_canonical.
Build: lake build SilverSightRRC 3006 jobs, 0 errors; q16-roundtrip 5949 jobs, 0 errors
