**STATUS: REJECTED** — moved to failed/ on 2026-07-04
**Reason:** The "degree on S²" framing is INVENTED — Rossby drift is a scalar quantity, not a winding number; the multiplexer has no measured multiplexing gain.
**Receipt:** Adversarial review (UNIFIED_THEORY_ADVERSARIAL_REVIEW.md §HCMR) — no experiment, no receipt; chiral premise killed by C3 run 019f2f07.

---

# HCMR × Chiral CRT Multiplexing: Performance Model

**Status:** CONNECTION — HCMR provides the hardware performance model for the multiplexer
**Date:** 2026-07-04
**Source:** `HardwareContentionMarkov.lean` (Research Stack, 0 sorries, complete)
**Integrates:** `CHIRAL_CRT_MULTIPLEXING.md`, `BRAIDSTORM_TREEBRAID_COUCH.md`

---

## 1. What HCMR Models

HardwareContentionMarkov.lean formalizes OISC throughput as a Markov chain:

| Structure | Meaning |
|-----------|---------|
| `CacheResidency` | Which cache level holds the data (L1/L2/L3/DRAM) |
| `ChainState` | Current state of the Markov chain (cache level + contention) |
| `OISCProgram` | The instruction stream being executed |

Self-loop probabilities (measured on EPYC KVM):

| Operation | Self-loop prob | Meaning |
|-----------|---------------|---------|
| SUBLEQ (word) | 0.823 | 82.3% chance of staying in same cache state |
| Cache-line AVX-512 | 0.885 | 88.5% — higher contention (larger working set) |
| Ring dispatch | 0.0 | 0% — always transitions (no contention) |

Throughput formula:
```
throughput = base_rate × (1 - self_loop_prob)
```

Cache miss rate: 2.5% per instruction (EPYC KVM, measured).

Theorems (proven, 0 sorries):
- Ring dispatch > word SUBLEQ > CL AVX-512 (throughput ordering)
- Higher self-loop = lower throughput = more contention

## 2. The Connection: HCMR = Performance Model for CRT Multiplexer

### 2.1 Markov Chain ↔ Chiral Multiplexer

The chiral CRT multiplexer (from CHIRAL_CRT_MULTIPLEXING.md) has:
- n/2 orthogonal channels (Sidon orthogonality theorem)
- Each channel = a chiral pair (L₀, L₁)
- Transitions between channels = braid crossings (σ_i)

HCMR models the SAME system at the hardware level:
- Each Markov state = a chiral channel (cache residency = which channel is active)
- Self-loop probability = how often the system stays on the same channel (contention)
- Mixing rate = how fast the multiplexer cycles through all channels

### 2.2 Self-Loop = Sidon Collision

The self-loop probability maps directly to the Sidon filter:

```
self_loop_prob = P(channel_i → channel_i) = P(Sidon collision)
               = fraction of chiral configurations that are degenerate
```

From the q-profile sweep:
- q > 1: 0% collisions (100% Sidon) → self_loop_prob ≈ 0 (ring dispatch)
- q < 1: 40-60% Sidon → self_loop_prob ≈ 0.4-0.6 (moderate contention)
- q = 1: degenerate → self_loop_prob ≈ 0.9+ (high contention, like CL AVX-512)

### 2.3 Throughput = Multiplexing Capacity

```
multiplexer_throughput = base_rate × (1 - collision_rate)
                       = base_rate × Sidon_pass_rate
```

For 8 strands (4 channels):
- If all 4 channels are Sidon-orthogonal (q > 1): throughput = base_rate × 1.0
- If 2/4 channels collide (q < 1): throughput = base_rate × 0.5
- If all collide (q = 1): throughput = base_rate × 0.1 (near-zero)

### 2.4 Cache Hierarchy ↔ TreeBraid Hierarchy

HCMR's cache levels map to TreeBraid's hierarchy:

| HCMR | TreeBraid | Meaning |
|------|-----------|---------|
| L1 cache | Leaf node | Individual chiral pair (finest scale) |
| L2/L3 cache | Internal node | Merged chiral group (coarser scale) |
| DRAM | Root | Full composed motion (coarsest scale) |

The cache miss rate (2.5%) = the probability that a TreeBraid merge
requires going to a coarser scale (DRAM = root level). This is the
"promotion cost" — when a fine-grained channel can't resolve, you
promote to a coarser merge.

## 3. What HCMR Adds to the Framework

### 3.1 The Missing Piece: Hardware Reality

The chiral CRT multiplexing theorems (Sidon Orthogonality, Multiplexing
Capacity, Hierarchical Encoding) are ALGEBRAIC — they tell you the
theoretical capacity. HCMR adds the PHYSICAL constraint:

- Theoretical capacity: n/2 channels (algebraic, exact)
- Actual throughput: n/2 × (1 - contention) (physical, measured)
- Contention depends on: cache behavior, working set size, hardware

HCMR is the bridge between the algebraic guarantee and the measured
performance. Without it, the multiplexer is a theoretical object.
With it, you can predict real throughput on specific hardware.

### 3.2 The COUCH Gate as Contention Filter

COUCH (couchStable) checks "pressure/hysteresis stability" — which in
HCMR terms is: "is the self-loop probability below threshold?"

```
COUCH_stable ⟺ self_loop_prob < threshold
             ⟺ Sidon pass rate > threshold
             ⟺ enough channels are non-degenerate
```

COUCH rejects configurations with high contention (high self-loop =
many Sidon collisions = few usable channels). This is the cheap
geometric pre-filter that prevents the expensive Sidon check from
running on degenerate configurations.

### 3.3 Measured Self-Loop Probabilities → Expected Multiplexer Performance

From HCMR's measured values, we can predict multiplexer performance:

| Configuration | Self-loop | Sidon pass rate | Usable channels (of 4) |
|---------------|-----------|-----------------|------------------------|
| Ring dispatch (q >> 1) | 0.0 | 100% | 4.0 |
| Word SUBLEQ (q ≈ 1.5) | 0.823 | ~18% | 0.7 |
| CL AVX-512 (q ≈ 1.0) | 0.885 | ~12% | 0.5 |

This predicts: the multiplexer performs best when q >> 1 (ring dispatch
regime), confirming the q-profile sweep finding (q > 1 = 100% Sidon).

The ring dispatch regime (self_loop = 0) corresponds to the CRT
configuration where all channels are perfectly Sidon-orthogonal —
every transition goes to a new channel, no collisions.

## 4. Porting HCMR to SilverSight

### 4.1 Current State

HCMR is in Research Stack (read-only archive, per AGENTS.md rule 1).
It needs to be ported to SilverSight as a clean port.

### 4.2 Port Target

```
formal/SilverSight/HCMR/
├── Defs.lean         # CacheResidency, ChainState, OISCProgram
├── Theorems.lean     # Throughput ordering (sorry stubs)
├── Discharge.lean    # No-drift gates
├── Solution.lean     # Clean API
└── Proofs/
    ├── Ordering/Basic.lean    # ring > SUBLEQ > AVX-512
    ├── Throughput/Basic.lean  # throughput = base × (1 - self_loop)
    └── CacheModel/Basic.lean  # 2.5% miss rate
```

Following the pipeline-math 5-file pattern (see PIPELINE_MATH_REFINEMENT.md).

### 4.3 Connection to CRTSidonN

The port should add a theorem connecting HCMR's mixing rate to the
CRT multiplexer's Sidon pass rate:

```
theorem crt_multiplexer_throughput
  (A : Finset ℕ) (hSidon : IsSidon A) (S : ℕ) (L₀ L₁ : ℕ)
  (hCoprime : Nat.Coprime L₀ L₁) ... :
  let sidon_pass_rate := <fraction of chiral configs that are Sidon>
  let throughput := base_rate × (1 - (1 - sidon_pass_rate))
  -- HCMR's formula with Sidon collision rate as self-loop prob
  throughput = base_rate × sidon_pass_rate
```

This would be the capstone theorem connecting the algebraic framework
(Sidon orthogonality) to the physical model (HCMR mixing rate).

## 5. claim_boundary

```
hcmr-crt-multiplexer:performance-model:connection
```

HCMR (HardwareContentionMarkov.lean) provides the hardware performance
model for the chiral CRT multiplexer. The connection:
- Markov self-loop probability = Sidon collision rate
- Mixing rate = multiplexer throughput
- Cache hierarchy = TreeBraid hierarchy
- COUCH gate = contention filter (rejects high self-loop configs)

HCMR is complete (0 sorries) in Research Stack. Port to SilverSight
following the pipeline-math 5-file pattern, with a capstone theorem
connecting Sidon pass rate to HCMR throughput.

**MEASURED:** self-loop probs (SUBLEQ=0.823, AVX-512=0.885, ring=0.0)
**MEASURED:** cache miss rate (2.5% per instruction, EPYC KVM)
**PREDICTED:** multiplexer throughput = base_rate × Sidon_pass_rate
**OPEN:** what is the actual Sidon pass rate on EPYC KVM hardware?